`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.04.2021 13:32:39
// Design Name:
// Module Name: axis_tlast_generator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axis_pipe_line
#(
////////////////////////////////////////////////////////////////////////////
//------------------------------- Inputs -----------------------------------
// Width of AXI stream interfaces in bits
parameter TDATA_WIDTH = 16,
// Propagate tkeep signal
parameter TKEEP_ENABLE = (TDATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter TKEEP_WIDTH = (TDATA_WIDTH/8),
// Propagate tid signal
parameter TID_ENABLE = 0,
// tid signal width
parameter TID_WIDTH = 8,
// Propagate tdest signal
parameter TDEST_ENABLE = 0,
// tdest signal width
parameter TDEST_WIDTH = 8,
// Propagate tuser signal
parameter TUSER_ENABLE = 1,
// tuser signal width
parameter TUSER_WIDTH = 1,
// Propagate tlast signal
parameter TLAST_ENABLE = 1,
// Output register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
parameter OUT_REG_TYPE = 2
)
(
//////////////////////////////////////////////////////////////////////////////////////
//------------------------------- System signals -------------------------------------
input aclk,
input aresetn,
//////////////////////////////////////////////////////////////////////////////////////
//------------------- (Slave) AXIS Payload Interface ------------------------
input wire [TDATA_WIDTH-1:0] s_axis_tdata,
input wire [TKEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [TID_WIDTH-1:0] s_axis_tid,
input wire [TDEST_ENABLE-1:0] s_axis_tdest,
input wire [TUSER_WIDTH-1:0] s_axis_tuser,
//////////////////////////////////////////////////////////////////////////////////////
//------------------- (Slave) AXIS Control Interface ------------------------
//////////////////////////////////////////////////////////////////////////////////////
//------------------- (Master) AXIS Payload Interface -----------------------
output wire [TDATA_WIDTH-1:0] m_axis_tdata,
output wire [TKEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [TID_WIDTH-1:0] m_axis_tid,
output wire [TDEST_ENABLE-1:0] m_axis_tdest,
output wire [TUSER_WIDTH-1:0] m_axis_tuser
);
reg [TDATA_WIDTH-1:0] m_axis_tdata_stage_01_ff = {TDATA_WIDTH{1'b0}};
reg [TKEEP_WIDTH-1:0] m_axis_tkeep_stage_01_ff = {TKEEP_WIDTH{1'b0}};
reg m_axis_tvalid_stage_01_ff = 1'b0;
reg m_axis_tlast_stage_01_ff = 1'b0;
reg [TID_WIDTH-1:0] m_axis_tid_stage_01_ff = {TID_WIDTH{1'b0}};
reg [TDEST_WIDTH-1:0] m_axis_tdest_stage_01_ff = {TDEST_WIDTH{1'b0}};
reg [TUSER_WIDTH-1:0] m_axis_tuser_stage_01_ff = {TUSER_WIDTH{1'b0}};
reg [TDATA_WIDTH-1:0] m_axis_tdata_stage_02_ff = {TDATA_WIDTH{1'b0}};
reg [TKEEP_WIDTH-1:0] m_axis_tkeep_stage_02_ff = {TKEEP_WIDTH{1'b0}};
reg m_axis_tvalid_stage_02_ff = 1'b0;
reg m_axis_tlast_stage_02_ff = 1'b0;
reg [TID_WIDTH-1:0] m_axis_tid_stage_02_ff = {TID_WIDTH{1'b0}};
reg [TDEST_WIDTH-1:0] m_axis_tdest_stage_02_ff = {TDEST_WIDTH{1'b0}};
reg [TUSER_WIDTH-1:0] m_axis_tuser_stage_02_ff = {TUSER_WIDTH{1'b0}};
reg [TDATA_WIDTH-1:0] m_axis_tdata_stage_03_ff = {TDATA_WIDTH{1'b0}};
reg [TKEEP_WIDTH-1:0] m_axis_tkeep_stage_03_ff = {TKEEP_WIDTH{1'b0}};
reg m_axis_tvalid_stage_03_ff = 1'b0;
reg m_axis_tlast_stage_03_ff = 1'b0;
reg [TID_WIDTH-1:0] m_axis_tid_stage_03_ff = {TID_WIDTH{1'b0}};
reg [TDEST_WIDTH-1:0] m_axis_tdest_stage_03_ff = {TDEST_WIDTH{1'b0}};
reg [TUSER_WIDTH-1:0] m_axis_tuser_stage_03_ff = {TUSER_WIDTH{1'b0}};
always @(posedge aclk) begin: proc_s_axis_tlast_rmap_cnt_ff
if(~aresetn) begin
m_axis_tvalid_stage_01_ff <= 0;
m_axis_tvalid_stage_02_ff <= 0;
m_axis_tvalid_stage_03_ff <= 0;
end else if(s_axis_tready == 1) begin
m_axis_tvalid_stage_01_ff <= s_axis_tvalid;
m_axis_tvalid_stage_02_ff <= m_axis_tvalid_stage_01_ff;
m_axis_tvalid_stage_03_ff <= m_axis_tvalid_stage_02_ff;
if(s_axis_tvalid == 1) begin
m_axis_tdata_stage_01_ff <= s_axis_tdata;
m_axis_tkeep_stage_01_ff <= s_axis_tkeep;
m_axis_tlast_stage_01_ff <= s_axis_tlast;
m_axis_tid_stage_01_ff <= s_axis_tid;
m_axis_tdest_stage_01_ff <= s_axis_tdest;
m_axis_tuser_stage_01_ff <= s_axis_tuser;
end
if(m_axis_tvalid_stage_01_ff == 1) begin
m_axis_tdata_stage_02_ff <= m_axis_tdata_stage_01_ff;
m_axis_tkeep_stage_02_ff <= m_axis_tkeep_stage_01_ff;
m_axis_tlast_stage_02_ff <= m_axis_tlast_stage_01_ff;
m_axis_tid_stage_02_ff <= m_axis_tid_stage_01_ff;
m_axis_tdest_stage_02_ff <= m_axis_tdest_stage_01_ff;
m_axis_tuser_stage_02_ff <= m_axis_tuser_stage_01_ff;
end
if(m_axis_tvalid_stage_02_ff == 1) begin
m_axis_tdata_stage_03_ff <= m_axis_tdata_stage_02_ff;
m_axis_tkeep_stage_03_ff <= m_axis_tkeep_stage_02_ff;
m_axis_tlast_stage_03_ff <= m_axis_tlast_stage_02_ff;
m_axis_tid_stage_03_ff <= m_axis_tid_stage_02_ff;
m_axis_tdest_stage_03_ff <= m_axis_tdest_stage_02_ff;
m_axis_tuser_stage_03_ff <= m_axis_tuser_stage_02_ff;
end
end
end
wire [TDATA_WIDTH-1:0] out_reg_s_axis_tdata;
wire [TKEEP_WIDTH-1:0] out_reg_s_axis_tkeep;
wire out_reg_s_axis_tvalid;
wire out_reg_s_axis_tready;
wire out_reg_s_axis_tlast;
wire [TID_WIDTH-1:0] out_reg_s_axis_tid;
wire [TDEST_ENABLE-1:0] out_reg_s_axis_tdest;
wire [TUSER_WIDTH-1:0] out_reg_s_axis_tuser;
assign out_reg_s_axis_tdata = m_axis_tdata_stage_03_ff;
assign out_reg_s_axis_tkeep = TKEEP_ENABLE ? m_axis_tkeep_stage_03_ff : {TKEEP_WIDTH{1'b1}};
assign out_reg_s_axis_tvalid = m_axis_tvalid_stage_03_ff;
assign out_reg_s_axis_tlast = TLAST_ENABLE ? m_axis_tlast_stage_03_ff : 1'b1;
assign out_reg_s_axis_tid = TID_ENABLE ? m_axis_tid_stage_03_ff : {TID_WIDTH{1'b0}};
assign out_reg_s_axis_tdest = TDEST_ENABLE ? m_axis_tdest_stage_03_ff : {TDEST_WIDTH{1'b0}};
assign out_reg_s_axis_tuser = TUSER_ENABLE ? m_axis_tuser_stage_03_ff : {TUSER_WIDTH{1'b0}};
assign s_axis_tready = out_reg_s_axis_tready;
axis_register
#(
// Width of AXI stream interfaces in bits
.TDATA_WIDTH(TDATA_WIDTH),
// Propagate tlast signal
.TLAST_ENABLE(TLAST_ENABLE),
// Propagate tid signal
.TID_ENABLE(TID_ENABLE),
// tid signal width
.TID_WIDTH(TID_WIDTH),
// Propagate tdest signal
.TDEST_ENABLE(TDEST_ENABLE),
// tdest signal width
.TDEST_WIDTH(TDEST_WIDTH),
// Propagate tuser signal
.TUSER_ENABLE(TUSER_ENABLE),
// tuser signal width
.TUSER_WIDTH(TUSER_WIDTH),
// Register type
// 0 to bypass, 1 for simple buffer, 2 for skid buffer
.REG_TYPE(OUT_REG_TYPE)
) axis_register_inst0
(
.clk(aclk),
.rst(aresetn),
/*
* AXI Stream input
*/
.s_axis_tdata(out_reg_s_axis_tdata),
.s_axis_tkeep(out_reg_s_axis_tkeep),
.s_axis_tvalid(out_reg_s_axis_tvalid),
.s_axis_tready(out_reg_s_axis_tready),
.s_axis_tlast(out_reg_s_axis_tlast),
.s_axis_tid(out_reg_s_axis_tid),
.s_axis_tdest(out_reg_s_axis_tdest),
.s_axis_tuser(out_reg_s_axis_tuser),
/*
* AXI Stream output
*/
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
Вот в моем представлении конвейер. Данные я пробросил условно, без математических операций. TREADY имею общий для всех стадий конвейера, как глобальный EN. TVALID свой для каждой стадии обработки. Правильно ли я понимаю, TVALID я двигаю по конвейеру только по TREADY? Вопрос по поводу сброса, достаточно будет сбросить только TVALID во всех стадиях или все триггеры сбрасывать?