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  1. Отмечусь со своим колхозом. gpio_macro.h: #ifndef __GPIO_MACRO_H_ #define __GPIO_MACRO_H_ /******************************************************************************* port *******************************************************************************/ // port A #define A0_PORT GPIOA #define A1_PORT GPIOA #define A2_PORT GPIOA #define A3_PORT GPIOA #define A4_PORT GPIOA #define A5_PORT GPIOA #define A6_PORT GPIOA #define A7_PORT GPIOA #define A8_PORT GPIOA #define A9_PORT GPIOA #define A10_PORT GPIOA #define A11_PORT GPIOA #define A12_PORT GPIOA #define A13_PORT GPIOA #define A14_PORT GPIOA #define A15_PORT GPIOA // port B #define B0_PORT GPIOB #define B1_PORT GPIOB #define B2_PORT GPIOB #define B3_PORT GPIOB #define B4_PORT GPIOB #define B5_PORT GPIOB #define B6_PORT GPIOB #define B7_PORT GPIOB #define B8_PORT GPIOB #define B9_PORT GPIOB #define B10_PORT GPIOB #define B11_PORT GPIOB #define B12_PORT GPIOB #define B13_PORT GPIOB #define B14_PORT GPIOB #define B15_PORT GPIOB // port C #define C0_PORT GPIOC #define C1_PORT GPIOC #define C2_PORT GPIOC #define C3_PORT GPIOC #define C4_PORT GPIOC #define C5_PORT GPIOC #define C6_PORT GPIOC #define C7_PORT GPIOC #define C8_PORT GPIOC #define C9_PORT GPIOC #define C10_PORT GPIOC #define C11_PORT GPIOC #define C12_PORT GPIOC #define C13_PORT GPIOC #define C14_PORT GPIOC #define C15_PORT GPIOC // port D #define D0_PORT GPIOD #define D1_PORT GPIOD #define D2_PORT GPIOD #define D3_PORT GPIOD #define D4_PORT GPIOD #define D5_PORT GPIOD #define D6_PORT GPIOD #define D7_PORT GPIOD #define D8_PORT GPIOD #define D9_PORT GPIOD #define D10_PORT GPIOD #define D11_PORT GPIOD #define D12_PORT GPIOD #define D13_PORT GPIOD #define D14_PORT GPIOD #define D15_PORT GPIOD // port E #define E0_PORT GPIOE #define E1_PORT GPIOE #define E2_PORT GPIOE #define E3_PORT GPIOE #define E4_PORT GPIOE #define E5_PORT GPIOE #define E6_PORT GPIOE #define E7_PORT GPIOE #define E8_PORT GPIOE #define E9_PORT GPIOE #define E10_PORT GPIOE #define E11_PORT GPIOE #define E12_PORT GPIOE #define E13_PORT GPIOE #define E14_PORT GPIOE #define E15_PORT GPIOE /******************************************************************************* pin *******************************************************************************/ // port A #define A0_PIN GPIO_PIN_0 #define A1_PIN GPIO_PIN_1 #define A2_PIN GPIO_PIN_2 #define A3_PIN GPIO_PIN_3 #define A4_PIN GPIO_PIN_4 #define A5_PIN GPIO_PIN_5 #define A6_PIN GPIO_PIN_6 #define A7_PIN GPIO_PIN_7 #define A8_PIN GPIO_PIN_8 #define A9_PIN GPIO_PIN_9 #define A10_PIN GPIO_PIN_10 #define A11_PIN GPIO_PIN_11 #define A12_PIN GPIO_PIN_12 #define A13_PIN GPIO_PIN_13 #define A14_PIN GPIO_PIN_14 #define A15_PIN GPIO_PIN_15 // port B #define B0_PIN GPIO_PIN_0 #define B1_PIN GPIO_PIN_1 #define B2_PIN GPIO_PIN_2 #define B3_PIN GPIO_PIN_3 #define B4_PIN GPIO_PIN_4 #define B5_PIN GPIO_PIN_5 #define B6_PIN GPIO_PIN_6 #define B7_PIN GPIO_PIN_7 #define B8_PIN GPIO_PIN_8 #define B9_PIN GPIO_PIN_9 #define B10_PIN GPIO_PIN_10 #define B11_PIN GPIO_PIN_11 #define B12_PIN GPIO_PIN_12 #define B13_PIN GPIO_PIN_13 #define B14_PIN GPIO_PIN_14 #define B15_PIN GPIO_PIN_15 // port C #define C0_PIN GPIO_PIN_0 #define C1_PIN GPIO_PIN_1 #define C2_PIN GPIO_PIN_2 #define C3_PIN GPIO_PIN_3 #define C4_PIN GPIO_PIN_4 #define C5_PIN GPIO_PIN_5 #define C6_PIN GPIO_PIN_6 #define C7_PIN GPIO_PIN_7 #define C8_PIN GPIO_PIN_8 #define C9_PIN GPIO_PIN_9 #define C10_PIN GPIO_PIN_10 #define C11_PIN GPIO_PIN_11 #define C12_PIN GPIO_PIN_12 #define C13_PIN GPIO_PIN_13 #define C14_PIN GPIO_PIN_14 #define C15_PIN GPIO_PIN_15 // port D #define D0_PIN GPIO_PIN_0 #define D1_PIN GPIO_PIN_1 #define D2_PIN GPIO_PIN_2 #define D3_PIN GPIO_PIN_3 #define D4_PIN GPIO_PIN_4 #define D5_PIN GPIO_PIN_5 #define D6_PIN GPIO_PIN_6 #define D7_PIN GPIO_PIN_7 #define D8_PIN GPIO_PIN_8 #define D9_PIN GPIO_PIN_9 #define D10_PIN GPIO_PIN_10 #define D11_PIN GPIO_PIN_11 #define D12_PIN GPIO_PIN_12 #define D13_PIN GPIO_PIN_13 #define D14_PIN GPIO_PIN_14 #define D15_PIN GPIO_PIN_15 // port E #define E0_PIN GPIO_PIN_0 #define E1_PIN GPIO_PIN_1 #define E2_PIN GPIO_PIN_2 #define E3_PIN GPIO_PIN_3 #define E4_PIN GPIO_PIN_4 #define E5_PIN GPIO_PIN_5 #define E6_PIN GPIO_PIN_6 #define E7_PIN GPIO_PIN_7 #define E8_PIN GPIO_PIN_8 #define E9_PIN GPIO_PIN_9 #define E10_PIN GPIO_PIN_10 #define E11_PIN GPIO_PIN_11 #define E12_PIN GPIO_PIN_12 #define E13_PIN GPIO_PIN_13 #define E14_PIN GPIO_PIN_14 #define E15_PIN GPIO_PIN_15 #define GPIO_PORT(x) x##_PORT #define GPIO_PIN(x) x##_PIN #define GPIO_READ_PIN(pin) HAL_GPIO_ReadPin(GPIO_PORT(pin), GPIO_PIN(pin)) #define GPIO_WRITE_PIN(pin, state) HAL_GPIO_WritePin(GPIO_PORT(pin), GPIO_PIN(pin), state) #define GPIO_TOGGLE_PIN(pin) HAL_GPIO_TogglePin(GPIO_PORT(pin), GPIO_PIN(pin)) #endif //__GPIO_MACRO_H_ main.c: #define LED_IND_GREEN_PIN B5 GPIO_WRITE_PIN(LED_IND_GREEN_PIN, GPIO_PIN_SET);
  2. Ставте другие датчики в такой тесноте.
  3. Плат сделал - тьма, все вручную, как по мне это не так долго и результат предсказуем. Аторазводчики таких вензелей загагулин понаделают... off: Мажно как-то смайлы настроить?
  4. LPC43XX + SDRAM

    Не должно влиять.
  5. MK10DN512 IAR проект

    Что мешает на сайте в SDK Builder'e сгенерить?
  6. Было лучше, рюшучки нафик никому не нужные, за ними суть теряется. Всё сливается воедино, контраста не хватает чтоли. Сорри
  7. LPC43XX + SDRAM

    Есть регистры чтение которых приводит к сбросу тех или иных бит, соответственно когда отладчик читает регистры это может влиять на работу програмы. В схеме есть отличия от кита в части подключения памяти? адреса/данные мешали?
  8. Печка - говно. Сверху плавится пластик разьемов, темнеет плата, при этом ближе к краям не не припаиваются микросхемы.
  9. LPC43XX + SDRAM

    Пример работы с SDRAM идущий в комплекте с вашей LPC4357-EVB не работает? Или у вас своя плата?
  10. Ну это образно, смайлик ведь поставил, типа функционал у программы большой.
  11. там есть функция для создания функции :biggrin: , а уж дописать пару байт.. СС2430 заставил изучить эту утиль подробно..
  12. Всегото галку надо было поставить. :smile3046: :08:
  13. Первый проект на плис и Lattice в часности. Полностью с нуля пытаюсь сосздать проект и залить в чип. На схему закинул один элемент 2И, входы соединил, in out, назначил пины, нажимаю Run, имею лог. Насколько я понял должен появится .jed файл, но его нет, в чем проблема может быть? Starting: "pgr_project save "D:/Projects/Soft/soft_Lattice_0/impl1/impl1.xcf"" Starting: "pgr_project close" sch2vlog -FPGA -i D:/Projects/Soft/soft_Lattice_0/main.sch -o D:/Projects/Soft/soft_Lattice_0/impl1/main.v -gui -msgset D:/Projects/Soft/soft_Lattice_0/promote.xml Done: completed successfully ************************************************************ ** Lattice Synthesis Engine ** ************************************************************ synthesis -f "Lattice_0_impl1_lattice.synproj" synthesis: version Diamond (64-bit) 3.10.2.115 Copyright © 1991-1994 by NeoCAD Inc. All rights reserved. Copyright © 1995 AT&T Corp. All rights reserved. Copyright © 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright © 2001 Agere Systems All rights reserved. Copyright © 2002-2017 Lattice Semiconductor Corporation, All rights reserved. Sat Sep 22 00:11:58 2018 Command Line: synthesis -f Lattice_0_impl1_lattice.synproj -gui INFO - Lattice Synthesis Engine Launched. Synthesis options: The -a option is MachXO2. The -s option is 2. The -t option is CSBGA132. The -d option is LCMXO2-1200ZE. Using package CSBGA132. Using performance grade 2. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200ZE ### Package : CSBGA132 ### Speed : 2 ########################################################## INFO - User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = main. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p D:/Projects/Soft/soft_Lattice_0 (searchpath added) -p C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00/data (searchpath added) -p D:/Projects/Soft/soft_Lattice_0/impl1 (searchpath added) -p D:/Projects/Soft/soft_Lattice_0 (searchpath added) Verilog design file = D:/Projects/Soft/soft_Lattice_0/impl1/main.v NGD file = Lattice_0_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/Lattice/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file d:/projects/soft/soft_lattice_0/impl1/main.v. VERI-1482 Analyzing Verilog file C:/Lattice/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): main INFO - d:/projects/soft/soft_lattice_0/impl1/main.v(3): compiling module main. VERI-1018 INFO - C:/Lattice/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(43): compiling module AND2. VERI-1018 Last elaborated design is main() Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/Lattice/lscc/diamond/3.10_x64/ispfpga. Package Status: Final Version 1.42. Top-level module name = main. WARNING - d:/projects/soft/soft_lattice_0/impl1/main.v(9): Removing unused instance . VDB-5034 GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks WARNING - No user .sdc file. Results of NGD DRC are available in main_drc.log. Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/Lattice/lscc/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - logical net 'GND_net' has no load. WARNING - DRC complete with 1 warnings. Design Results: 7 blocks expanded completed the first expansion All blocks are expanded and NGD expansion is successful. Writing NGD file Lattice_0_impl1.ngd. ################### Begin Area Report (main)###################### Number of register bits => 0 of 1595 (0 % ) AND2 => 1 GSR => 1 IB => 1 OB => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 0 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : f2_c, loads : 2 Net : o_c, loads : 1 Net : o, loads : 0 ################### End Clock Report ################## Peak Memory Usage: 49.711 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.265 secs -------------------------------------------------------------- Done: completed successfully ************************************************************ ** Map Design ** ************************************************************ map -a "MachXO2" -p LCMXO2-1200ZE -t CSBGA132 -s 2 -oc Commercial "Lattice_0_impl1.ngd" -o "Lattice_0_impl1_map.ncd" -pr "Lattice_0_impl1.prf" -mp "Lattice_0_impl1.mrp" -lpf "D:/Projects/Soft/soft_Lattice_0/impl1/Lattice_0_impl1.lpf" -lpf "D:/Projects/Soft/soft_Lattice_0/Lattice_0.lpf" -c 0 map: version Diamond (64-bit) 3.10.2.115 Copyright © 1991-1994 by NeoCAD Inc. All rights reserved. Copyright © 1995 AT&T Corp. All rights reserved. Copyright © 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright © 2001 Agere Systems All rights reserved. Copyright © 2002-2017 Lattice Semiconductor Corporation, All rights reserved. Process the file: Lattice_0_impl1.ngd Picdevice="LCMXO2-1200ZE" Pictype="CSBGA132" Picspeed=2 Remove unused logic Do not produce over sized NCDs. Part used: LCMXO2-1200ZECSBGA132, Performance used: 2. Loading device for application map from file 'xo2c1200.nph' in environment: C:/Lattice/lscc/diamond/3.10_x64/ispfpga. Package Status: Final Version 1.42. Running general design DRC... Removing unused logic... Optimizing... Design Summary: Number of registers: 0 out of 1595 (0%) PFU registers: 0 out of 1280 (0%) PIO registers: 0 out of 315 (0%) Number of SLICEs: 0 out of 640 (0%) SLICEs as Logic/ROM: 0 out of 640 (0%) SLICEs as RAM: 0 out of 480 (0%) SLICEs as Carry: 0 out of 640 (0%) Number of LUT4s: 0 out of 1280 (0%) Number used as logic LUTs: 0 Number used as distributed RAM: 0 Number used as ripple logic: 0 Number used as shift registers: 0 Number of PIO sites used: 2 + 4(JTAG) out of 105 (6%) Number of block RAMs: 0 out of 7 (0%) Number of GSRs: 0 out of 1 (0%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 1 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 0 Number of Clock Enables: 0 Number of LSRs: 0 Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net f2_c: 1 loads Number of warnings: 0 Number of errors: 0 Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 36 MB Dumping design to file Lattice_0_impl1_map.ncd. ncd2vdb "Lattice_0_impl1_map.ncd" ".vdbs/Lattice_0_impl1_map.vdb" Loading device for application ncd2vdb from file 'xo2c1200.nph' in environment: C:/Lattice/lscc/diamond/3.10_x64/ispfpga. Done: completed successfully ************************************************************ ** Place & Route Design ** ************************************************************ mpartrce -p "Lattice_0_impl1.p2t" -f "Lattice_0_impl1.p3t" -tf "Lattice_0_impl1.pt" "Lattice_0_impl1_map.ncd" "Lattice_0_impl1.ncd" ---- MParTrce Tool ---- Removing old design directory at request of -rem command line option to this program. par -f Lattice_0_impl1.p2t.tmp0 Lattice_0_impl1_map.ncd Lattice_0_impl1.dir\5_1.dir Lattice_0_impl1.prf -gui Output design is: Lattice_0_impl1 Output DIR is: . Preference file is: Lattice_0_impl1.prf Exiting mpartrce with exit code 0 Done: completed successfully
  14. ПО на МПП

    EvilWrecker рубанул правду-матку. :maniac: