[cms 0]

OFF: Ну вот меня вроде бы разбанили. Могу писать дальше.

 

29 января 2009 приняли новую ревизию VHDL IEEE1076.

Посмотрел новый стандарт. Изменений много, но ИМХО до уровня SystemVerilog VHDL-2008 не подрос.

 

 

Changes from IEEE Std 1076-2002:

 

This annex lists those clauses that have been changed from IEEE Std 1076-2002, during its revision. The

clause numbers are from this present revision. Note that purely editorial changes, such as typographic error

corrections and changes made to conform to IEEE terminological rules, are not listed.

 

Clause 1

 

— 1.3.5: Describes incorporation of PSL.

 

Clause 3

 

— 3.2.2: Descriptions of generic (formerly 1.1.1.1) and ports (formerly 1.1.1.2) moved to 6.5.6.2 and

6.5.6.3, respectively.

— 3.2.3: Addition of subprogram instantiations, package declarations and instantiations, and PSL

declarations in entity declarative part.

— 3.2.4: Addition of PSL directives in entity statement part.

— 3.3.1: Change to scope of architecture body.

— 3.3.2: Addition of subprogram instantiations, package declarations and instantiations, and PSL

declarations in block declarative part.

— 3.4.1: Addition of verification unit binding indication in configuration declaration.

— 3.4.2: Rules for configuring generate statements extended to include if-generate and case-generate

statements; addition of specification that discrete range in a generate specification be static.

— 3.4.3: Addition of verification unit binding indication in component configuration.

 

Clause 4

 

— 4.2.1: Addition of subprogram header; description of uninstantiated and generic-mapped

subprograms.

— 4.2.2.2: Changes for VHPI; changes to subtype rules.

— 4.2.2.3: Changes to subtype rules.

— 4.3: Addition of subprogram instantiations, package declarations and instantiations, and PSL

declarations in subprogram declarative part; additional rules relating to uninstantiated subprograms.

— 4.4: New subclause describing subprogram instantiation declarations.

— 4.5.2: Extension to operator overloading rules.

— 4.5.3: Extension to rule relating to appearance of a signature.

— 4.6: Revision relating to new array subtype rules; other clarifications and corrections.

— 4.7: Addition of package header; description of uninstantiated and generic-mapped packages;

addition of subprogram instantiations, package declarations and instantiations, and PSL declarations

in package declarative part; rules relating to packages appearing other than as a design unit.

— 4.8: Addition of subprogram instantiations, package declarations and instantiations, PSL

declarations, and attribute declarations and specifications in package body declarative part; rules

relating to packages appearing other than as a design unit.

— 4.9: New subclause describing package instantiation declarations.

— 4.10: Addition of profile conformance, distinguished from lexical conformance.

 

Clause 5

 

— 5.1: Clarification of predefined operations; definition of unconstrained, partially constrained, and

fully constrained composite subtypes.

— 5.2.1: Clarification of range constraints and range bounds of scalar types.

— 5.2.2: Clarification of enumeration literal declaration.

— 5.2.4.2: Change to definition of resolution limit.

— 5.2.6: New subclause describing predefined operations on scalar types.

— 5.3.2.1: Extensions to array type definitions; addition of array constraints, extending index

constraints.

— 5.3.2.2: Extension and clarification of rules relating to index ranges and array subtypes.

— 5.3.2.3: Addition of new predefined array types.

— 5.3.2.4: New subclause describing predefined operations on array types.

— 5.3.3: Extensions to rules for record type definitions; addition of record constraints.

— 5.4.1: Clarification and revision of type rules.

— 5.5.1: Clarification and revision of type rules.

— 5.5.2: Addition of FLUSH operation; minor revisionof type rule.

— 5.6.2: Addition of subprogram instantiation in protected type declarative part; clarification of type rules.

— 5.6.3: Addition of subprogram instantiations, and package declarations and instantiations in

protected type body declarative part.

— 5.7: New subclause describing string representations, formerly in 16.4.

 

Clause 6

 

— 6.1: Addition of subprogram instantiations, package instantiations, PSL verification units, and PSL

declarations in declarations; clarification of the definition of a declaration; added definition of a

designator.

— 6.2: Additional rules for generic types and type declarations.

— 6.3: Extension of subtype indication relating to constraints and resolution functions.

— 6.4.1: Change in terminology for generics.

— 6.4.2.2: Clarifications.

— 6.4.2.3: Revision of rules relating to resolved signals; clarification of type rules.

— 6.4.2.4: Revision of rules relating to appearance of variable declarations.

— 6.5: Former 4.3.2 promoted to this subclause.

— 6.5.1: Revision of definition of interface declaration.

— 6.5.2: Descriptions of interface objects demoted into this new subclause; revisions to rules relating to

interface constants; revision of rules relating to modes.

— 6.5.3: New subclause describing interface type declarations.

— 6.5.4: New subclause describing interface subprogram declarations.

— 6.5.5: New subclause describing interface package declarations.

— 6.5.6.1: Revisions relating to new classes of interface declarations and new places where interface

lists may appear.

— 6.5.6.2: New subclause containing descriptions from former 1.1.1 and 1.1.1.1; extensions relating to

generic types, subprograms, and packages.

— 6.5.6.3: New subclause containing descriptions from former 1.1.1 and 1.1.1.2; extension relating to

non-static expression associated with a port; extension relating to port modes.

— 6.5.7.1: Extensions relating to new classes of interface declarations and new places where

association lists may appear; extensions to actual designators; clarifications of rules for type

conversions and conversion functions.

— 6.5.7.2: New subclause containing descriptions from former 5.2.1.2; extensions relating to new

classes of generics and new places where generic map aspects may appear.

— 6.5.7.3: New subclause containing descriptions from former 5.2.1.2.

— 6.6: Former 4.3.3 promoted to this subclause.

— 6.6.2: Extension to type rules; addition of rules relating to external names.

— 6.6.3: Clarification of rules relating to types.

— 6.7: Clarification of type rules.

— 6.11: New subclause describing PSL clock declarations.

 

Clause 7

 

— 7.2: Additional entity classes defined; revision of rules relating to specification of named entities;

revision of rules relating to decoration of packages.

— 7.3.1: Addition of verification unit binding indication in configuration specification.

— 7.3.2: Extensions relating to new classes of interface declarations; clarification of error condition;

descriptions in former 5.2.1.2 moved to 6.5.7.

— 7.3.3: Clarification.

— 7.3.4: New subclause describing verification unit binding indications.

— 7.4: Clarification of type rules.

 

Clause 8

 

— 8.1: Addition of character literals and external names; deleted rule relating to access-typed prefix.

— 8.3: Revision of expanded name rules relating to architecture bodies; addition of protected type

definition in expanded name; clarification of prefix for a method name.

— 8.6: Clarification of predefined attribute names.

— 8.7: New subclause describing external names.

 

Clause 9

 

— 9.1: Addition of operators.

— 9.2.1: Addition of operators and predefined operations.

— 9.2.2: Extensions relating to operand types and unary forms.

— 9.2.3: Addition of matching relational operators.

— 9.2.4: Clarification of rule for index ranges.

— 9.2.5: Correction of terminology relating to index ranges.

— 9.2.7: Extension relating to operand types.

— 9.2.9: New subclause describing condition operator.

— 9.3.2: Revision of rules relating to null string literals; correction of terminology relating to index

ranges.

— 9.3.3.1: Clarification of rules relating to discrete range choices.

— 9.3.3.3: Extensions relating to expressions of the type of the aggregate; revision and correction of

terminology in rules relating to index ranges.

— 9.3.4: Additional rule relating to uninstantiated subprograms; clarification of parameter index range

rules.

— 9.3.5: Revision of rule describing effect of type qualification.

— 9.3.6: Extension allowing conversion between array types with different index types; addition of

rules relating to null arrays; extension relating to array types with undefined index ranges.

— 9.3.7: Extension to rules relating to constraints.

— 9.4.2: Addition of operations defined in STD_LOGIC_1164; revision and extension to rules

describing locally static primaries, constraints, and subtypes.

— 9.4.3: Revision and extension to rules describing globally static primaries, constraints and subtypes.

 

Clause 10

 

— 10.2: Generalization of type of a condition; extended applicability of rules for forming sensitivity

list.

— 10.3: Revision of rules relating to messages and severity level.

— 10.4: Revision of rules relating to messages and severity level.

— 10.5: Addition of force and release assignment; addition of simple, conditional and selected signal

assignment.

— 10.5.2: New subclause containing descriptions from former 8.4, describing simple signal assignment,

force and release.

— 10.5.2.2: Former 8.4.1; clarification of subtype rules; addition of rules relating to force and release.

— 10.5.3: New subclause containing descriptions from former 9.5.1 describing conditional signal

assignment, force and release.

— 10.5.4: New subclause containing descriptions from former 9.5.2 describing selected signal

assignment, force and release, and matching selected signal assignment.

— 10.6: Addition of simple, conditional, and selected variable assignment.

— 10.6.2: New subclause containing descriptions from former 8.5, describing simple variable

assignment; clarification of subtype rules; extension dealing with VHPI force; deleted text originally

intended to be non-normative; addition of rule relating to aggregate targets.

— 10.6.2.2: Former 8.5.1; revision of rules relating to composite target.

— 10.6.3: New subclause describing conditional variable assignment.

— 10.6.4: New subclause describing selected variable assignment.

— 10.7: Extension relating to uninstantiated subprograms; revision of rules relating to index ranges of

parameters.

— 10.9: Addition of matching case statement; revision of rules relating to choices and expression

subtype.

— 10.13: Revision to rules relating to result subtype.

 

Clause 11

 

— 11.1: Addition of PSL directive as a concurrent statement.

— 11.3: Addition of all in a process sensitivity list; addition of subprogram instantiations, and package

declarations and instantiations in process declarative part.

— 11.5: Addition of rule disambiguating assertions.

— 11.6: Revision of concurrent signal assignment rules; former 9.5.1 moved to 10.5.3; former 9.5.2

moved to 10.5.4.

— 11.7.2: Revision of rules for equivalent block statements.

— 11.7.3: Revision of rules for equivalent block statements.

— 11.8: Addition of if-generate and case-generate statements.

 

Clause 12

 

— 12.1: Revision of rules relating to declaration of architecture bodies.

— 12.2: Revision of rules relating to scope of architecture names; additional rules relating to

uninstantiated declarations and PSL verification units.

— 12.3: Revision of visibility rule determining more than one meaning; additional rules relating to

packages, architecture names, subprogram and package instantiation, alternative labels of generate

statements, PSL verification units, PSL declarations and PSL directives; revision of rules for

visibility of interface objects; revision of visibility by selection rules; revision of homograph

definition and hiding rules.

— 12.4: Revision of rules relating identified declarations; revision of rules relating to direct visibility;

additional rule relating to context declarations.

— 12.5: Additional rule relating to subprogram instantiation.

 

Clause 13

 

— 13.1: Addition of package instantiation declaration, context declaration and PSL verification unit as

primary units; additional rule relating to context declarations.

— 13.2: Additional rules relating to context declarations; addition of library IEEE and new packages.

— 13.3: New subclause describing context declarations.

— 13.4: Addition of context references.

 

Clause 14

 

— 14.2: Additional rules relating to VHPI and PSL verification units; extension to rule relating to toplevel

generics; additional rules relating to package instantiations; revision to order of elaboration of

drivers; additional rules relating to external names.

— 14.3.1: Additional rules relating to package and subprogram headers.

— 14.3.2: Revision of order of elaboration.

— 14.3.3: Revision of order of elaboration; additional rules for new classes of generics.

— 14.3.4: Revision of order of elaboration.

— 14.3.5: Revision of order of elaboration; additional rules relating to association with non-static

expressions; clarification of subtype rules.

— 14.4.1: Additional rules relating to VHPI.

— 14.4.2: Additional rule relating to PSL declarations.

— 14.4.2.2: Additional rules relating to subprogram instantiations.

— 14.4.2.3: Revision of rules relating to composite type declarations.

— 14.4.2.4: Additional rules relating to constraints.

— 14.4.2.5: Revision of rules relating to composite object declarations; clarified applicability of rules.

— 14.4.2.6: Revision of rule relating to composite alias declarations.

— 14.4.2.9: New subclause describing elaboration of packages.

— 14.4.3.2: Revision of rules relating to composite attributes.

— 14.5.1: Additional rules relating to VHPI and to PSL directives.

— 14.5.3: Additional rules relating to if-generate and case-generate statements.

— 14.5.5: Revision to order of elaboration of drivers.

— 14.6: Revision of order of elaboration of parameters; additional rules relating to VHPI.

— 14.7.1: Additional rule relating to PSL directives; revision of rules relating to kernel variables.

— 14.7.2: Revision and extension of rules relating to kernel variables, to update of drivers, and to VHPI.

— 14.7.3: Revision and extension of rules relating to force and release, update of drivers and signals,

kernel variables, and VHPI.

— 14.7.4: Additional rules relating to VHPI.

— 14.7.5: Former 12.6.4 partitioned into subclauses.

— 14.7.5.1: New subclause containing description of initialization from former 12.6.4; revised rules for

determining Tn factored out.

— 14.7.5.2: New subclause containing description of initialization from former 12.6.4; additional rules

for VHPI and for force and release; revision of rules relating to order of signal update; additional

rules relating to PSL directives.

— 14.7.5.3: New subclause containing description of the simulation cycle from former 12.6.4;

additional rules for VHPI and for force and release; revision of rules relating to order of signal

update; additional rules relating to PSL directives.

 

Clause 15

 

— Clause 15: Former 13.10 deleted.

— 15.2: Additional rules relating to tool directives and to PSL; revision of character set usage;

clarification of case correspondence.

— 15.3: Additional rules relating to tool directives and to PSL; additional delimiters.

— 15.8: Addition of length, signed and unsigned bases, decimal base, and non-digit characters.

— 15.9: Addition of delimited comments.

— 15.10: Additional reserved words defined; additional rules for PSL.

— 15.11: New subclause describing tool directives .

 

Clause 16

 

— 16.2: Additional rule relating to predefined attributes that are functions; clarification of atribute

kinds; revision of rules for 'VALUE, 'IMAGE, 'POS, 'LENGTH, 'ASCENDING, and

'LAST_VALUE; revision of rules for attributes of arrays; addition of 'SUBTYPE and 'ELEMENT;

additional rules for 'PATH_NAME and 'INSTANCE_NAME.

— 16.3: Additional types and operations defined.

— 16.4 Additional operations defined; description of string representation moved to 5.7.

— 16.5: New subclause describing standard environment package.

— 16.6: New subclause describing standard mathematical packages, formerly in IEEE 1076.2-1996

[b11].

— 16.7: New subclause describing standard multivalue logic package, formerly in IEEE 1164-1993

[b16].

— 16.8: New subclause describing standard synthesis packages, formerly in IEEE 1076.3-1997 [b12].

— 16.9: New subclause describing standard synthesis context declarations.

— 16.10: New subclause describing fixed-point packages.

— 16.11: New subclause describing floating-point packages.

 

Clauses 17–23

 

— New clauses describing VHPI.

 

Clause 24

 

— New clause describing standard tool directives.

 

Annex A

 

— New annex describing accompanying files.

 

Annex B

 

— New annex describing VHPI header files and extension mechanisms.

 

Annex C

 

— Formerly Annex A; revision of productions and addition of new productions.

 

Annex D

 

— Formerly Annex C; additional item relating to format specifiers.

 

Annex F

 

— Formerly Annex E; deletion of entries.

 

Annex G

 

— New annex describing use of standard packages.

 

Annex H

 

— New annex describing use of protect directive.

 

Annex I

 

— Formerly Annex B; revision of entries and addition of new entries.

 

Annex J

 

— Formerly Annex F; revision of entries and addition of new entries.

[Sefo 0]

Ура! Товарищи! :)

[cms 0]

Ура! Товарищи! :)

 

да, да, спасибо, я тоже рад, что меня разбанили... :maniac:

[CaPpuCcino 0]

29 января 2009 приняли новую ревизию VHDL IEEE1076.

везёт вам - generic types ввели

здесь можно поглядеть информацию о нововведениях уже в переваренном виде http://www.doulos.com/knowhow/vhdl_designe...uide/vhdl_2008/

[cms 0]

везёт вам - generic types ввели

здесь можно поглядеть информацию о нововведениях уже в переваренном виде http://www.doulos.com/knowhow/vhdl_designe...uide/vhdl_2008/

 

Спасибо за ссылку, Дулос как всегда рулит.

 

Насчет generic types завидовать не надо, у вас тоже есть механизм параметризованных классов, позволяющий передавать типы как параметр. И VCS 2008.12 это уже вроде как поддерживает.

[des00 25]

Спасибо за ссылку, Дулос как всегда рулит.

 

Насчет generic types завидовать не надо, у вас тоже есть механизм параметризованных классов, позволяющий передавать типы как параметр. И VCS 2008.12 это уже вроде как поддерживает.

 

ндя не прошло и 20ти лет, как стало очевидна необходимость Hierarchical names, механизма force/release, нормального условного генерейта и блочных комментариев, а ведь язык то хороший, не понятно зачем нужно было его так тормозить. %))

 

жаль что не ввели макросы и используемые блочные комментарии позабавили, могли бы придумать что-то пооригинальнее прямого заимствования.

 

 

ЗЫ. откатываться назад не буду, меня SV почти полностью устраивает

[Maverick_ 15]

Может быть кто-то поделиться данным стандартом (VHDL: IEEE1076-2008) :1111493779:

ЗЫ желательно полный вариант и в pdf формате

[LeonY 0]

Ну дождались...

Ау кого-нибудь есть инфа о планах поддержки стандарта основными производителями софта?

[warrior-2001 0]

Ментор вроде заявлял на одной из презентаций, что в ближайших версиях САПР vhdl2008 будет поддержан полностью. Однако меня терзают смутные сомнения, ибо

FPGAdv полностью не поддерживает SV, чего уж говорить о новом vhdl2008. Да и на официальном сайте я сегодня не нашёл высказываний о поддержке vhdl2008.

А ведь писали об этой поддержке.

Альтера тоже сразу не сможет полностью поддержать vhdl2008.

Разве что Xilinx. Но с их САПРами я не работаю...

Изменено 16 марта, 2009 пользователем warrior-2001

[des00 25]

Разве что Xilinx. Но с их САПРами я не работаю...

 

эти точно врядли, они SV прикрутить отказываются. Скорее всего синопсис что то в своих тулзах реализует .

[SM 0]

Альтера тоже сразу не сможет полностью поддержать vhdl2008.

Разве что Xilinx. Но с их САПРами я не работаю...

Уж альтера-то быстрее поддержит, чем xil, по крайней мере поддержку SV они начали сразу по его появлению.

 

Другое дело, непонятно, кому нужна эта конкурренция. Сделали в SV все необходимое, ну и нафига дотягивать за уши туда другие языки? Одна головная боль производителям софта.

 

Скорее всего синопсис что то в своих тулзах реализует .

Эти-то тем более. Они чуть ли не основные продвигатели SV.

[Oldring 0]

Разве что Xilinx.

 

Xil еще 2002 не поддержал

[CaPpuCcino 0]

Сделали в SV все необходимое, ну и нафига дотягивать за уши туда другие языки? Одна головная боль производителям софта.

ну почему же боль, больше похоже на коммерческий ход - американцы на это мастаки. у меня есть впечатление что они растягивают языки - СВ в сторону верификации, ВХДЛ - в сторону мощного РТЛ синтеза. тормозили 10 лет ВХДЛ, теперь СВ будут столько же тормозить - то что планируется осенью по СВ-2009 вообще-то просто смешно (такое впечатление, что 5 лет в носу ковырялись - не одного насущного вопроса не решили).

[cms 0]

ну почему же боль, больше похоже на коммерческий ход - американцы на это мастаки. у меня есть впечатление что они растягивают языки - СВ в сторону верификации, ВХДЛ - в сторону мощного РТЛ синтеза. тормозили 10 лет ВХДЛ, теперь СВ будут столько же тормозить - то что планируется осенью по СВ-2009 вообще-то просто смешно (такое впечатление, что 5 лет в носу ковырялись - не одного насущного вопроса не решили).

 

Хм. Попытался сейчас придумать, чем VHDL мощнее SV в части синтеза. Не придумал.

Возможно строгая типизация?

 

Одно только то, что в VHDL нет препроцессорных директив убивает гибкость RTL.

Чего только стоит отсутствие директивы `include.

[CaPpuCcino 0]

Насчет generic types завидовать не надо, у вас тоже есть механизм параметризованных классов, позволяющий передавать типы как параметр. И VCS 2008.12 это уже вроде как поддерживает.

...

Хм. Попытался сейчас придумать, чем VHDL мощнее SV в части синтеза. Не придумал.

Возможно строгая типизация?

не хотел эту тему развивать, потому как не о СВ изначально речь. в СВ по сравнению с нынешним ВХДЛ очень серьёзно нехватает темплетезации (структур данных, функций). частично эта тема обсуждалась здесь - http://electronix.ru/forum/index.php?showtopic=40038 . а темплетизация - это, на мой взгляд, следующий шаг абстракции данных (как введение структур, объединений, массивов объектов - следущий шаг после битовых векторов).

ну, а строгая типизация (к месту, и... но в основном не к месту), для меня, если честно, наоборот основной раздражитель в ВХДЛ