aliceLiddell 0 2 мая Опубликовано 2 мая (изменено) · Жалоба Помогите пожалуйста исправить программу. Модули с 4 по 7 и с 9 по 11 не подходят к основной программе, хотя в них ошибок нет. Схема простейшая для станка на плазме. Не работает даже синтез этих модулей совместно, хотя по отдельности их проверил я уже не один раз. Спойлер `timescale 1ps/1ps ////////////////////////////////////////////////////////////////////////////////// //Company: //Engineer: // //CreateDate:19.04.202406:34:41 //DesignName: //ModuleName:main //ProjectName: //TargetDevices: //ToolVersions: //Description: // //Dependencies: // //Revision: //Revision0.01-FileCreated //AdditionalComments: // ////////////////////////////////////////////////////////////////////////////////// module main( input CLK_pin, input UART_RX_deb_pin, output UART_TX_deb_pin, output CLK_deb_pin, output [15:0] DDR_addr, output [2:0] DDR_ba, output DDR_cas_n, output DDR_ck_n, //1 output DDR_ck_p, //2 output DDR_cke, //3 output DDR_cs_n, ///4 input DDR_dm, ////5 inout [7:0] DDR_dq, /////6 inout DDR_dqs_n, ////7 inout DDR_dqs_p, ////8 output DDR_odt, /////9 output DDR_ras_n, ///10 output DDR_reset_n, //11 output DDR_we_n, ////12 input PCIe_RX_p_pin, input PCIe_RX_n_pin, output PCIe_TX_p_pin, output PCIe_TX_n_pin, output PCIe_RST_pin, output PCIe_CLK_pin, output DAC_CLK_pin, output DAC1_DAT_pin, output DAC1_CLRn_pin, output DAC1_LDACn_pin, output DAC1_CSn_pin, output DAC2_DAT_pin, output DAC2_CLRn_pin, output DAC2_LDACn_pin, output DAC2_CSn_pin, input MCLK_pin, input MDAT_pin, input VP_pin, input VN_pin, input [7:0] ETH_RXd_pin, output[7:0] ETH_TXd_pin, input USART1iA_pin, input USART1iB_pin, output USART1oA_pin, output USART1oB_pin, input USART2iA_pin, input USART2iB_pin, output USART2oA_pin, output USART2oB_pin, output FB_CLK_pin, input [11:0] FB_pin, output eth_col_pin, output eth_cors_pin, input eth_rx_clk_pin, input eth_rx_dv_pin, output eth_rx_err_pin, input eth_tx_clk_pin, input eth_tx_en_pin, output eth_tx_err_pin ); //Wires wire [53:0 ]MIO; wire [63:0] gpio_o; wire [63:0] gpio_i; wire CLK_o; wire CLK_usart; wire [11:0] feedback; wire [11:0] KvMETER1; wire [11:0] KvMETER2; wire [11:0] KvMETER3; wire ovp_o; reg [11:0] KvM1; wire clk_i; wire rst_i; wire clk_m; wire CLK_01; wire [3:0] eth_txd; wire [3:0] eth_rxd; wire GMII_ETHERNET_1_col; wire GMII_ETHERNET_1_cors; wire GMII_ETHERNET_1_rx_clk; wire GMII_ETHERNET_1_rx_dv; wire GMII_ETHERNET_1_rx_er; wire GMII_ETHERNET_1_tx_clk; wire GMII_ETHERNET_1_tx_en; wire GMII_ETHERNET_1_tx_er; wire USART_Rx; wire USART_Tx; wire USART2_Rx; wire USART2_Tx; wire err1; wire err2; wire pwr_on; wire interrupter; wire temp_req; wire [15:0] temp; wire temp_RDy; wire [7:0] TTemp1; wire [7:0] TTemp2; wire qcw_on; wire [12:0] audio_deamon; wire [7:0] audio_da_volume; wire [17:0] coil_freque_o;//эяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэя wire int;//эяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэя.0эяэяэяэяэяэяэяэяэяэяэяэя. wire [31:0] spark; wire sh;//эяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэяэя wire [17:0] freq_o; wire outa_b; wire outb_b; wire PCIe_RX_p; wire PCIe_RX_n; wire PCIe_TX_p; wire PCIe_TX_n; wire PCIe_RST; wire PCIe_CLK; wire mdat_i; wire mclk_i; wire dac_clk_o; wire dac1_dat_o; wire dac1_ldacn_o; wire dac1_clrn_o; wire dac1_csn_o; wire dac2_dat_o; wire dac2_ldacn_o; wire dac2_clrn_o; wire dac2_csn_o; wire FIXED_IO_ddr_vrn; wire FIXED_IO_ddr_vrp; wire CLK_uart; wire UART_RX_INT; wire UART_TX_INT; wire UART_RX_deb; wire UART_TX_deb; //Buffers BUFGCE_1 BUFGCE_1_inst(.O(clk_i), .CE(1), .I(CLK_pin)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_UART_RX (.I(UART_RX_deb_pin), .O(UART_RX_deb)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_UART_TX(.O(UART_TX_deb_pin), .I(UART_TX_deb)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_PCIe_TXp(.I(PCIe_TX_p), .O(PCIe_TX_p_pin)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_PCIe_TXn(.I(PCIe_TX_n), .O(PCIe_TX_n_pin)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_PCIe_RXp(.I(PCIe_RX_p_pin), .O(PCIe_RX_p)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_PCIe_RXn(.I(PCIe_RX_n_pin), .O(PCIe_RX_n)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_ETH_COL(.I(GMII_ETHERNET_1_col), .O(eth_col_pin)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_ETH_COR(.I(GMII_ETHERNET_1_cors), .O(eth_cors_pin)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_ETH_RCL(.I(eth_rx_clk_pin), .O(GMII_ETHERNET_1_rx_clk)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_ETH_DV(.I(eth_rx_dv_pin), .O(GMII_ETHERNET_1_rx_dv)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_ETH_ERR(.I(GMII_ETHERNET_1_rx_er), .O(eth_tx_err_pin)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_ETH_TCK(.I(eth_tx_clk_pin), .O(GMII_ETHERNET_1_tx_clk)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_ETH_TEN(.I(eth_tx_en_pin), .O(GMII_ETHERNET_1_tx_en)); IBUFDS #(.DIFF_TERM("FALSE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IDS1_usart(.O(USART_Rx), .I(USART1iA_pin), .IB(USART1iB_pin)); OBUFDS #(.IOSTANDARD("DEFAULT"), .SLEW("FAST")) ODS_usart(.O(USART1oA_pin), .OB(USART1oB_pin), .I(USART_Tx)); IBUFDS #(.DIFF_TERM("FALSE"), .IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IDS2_usart(.O(USART2_Rx), .I(USART2iA_pin), .IB(USART2iB_pin)); OBUFDS #(.IOSTANDARD("DEFAULT"), .SLEW("FAST")) OD2_usart(.O(USART2oA_pin), .OB(USART2oB_pin), .I(USART2_Tx)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_MDAT(.O(mdat_i), .I(MDAT_pin)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_MCLK(.O(mclk_i), .I(MCLK_pin)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC_CLK(.O(DAC_CLK_pin), .I(dac_clk_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC1_DAT(.O(DAC1_DAT_pin), .I(dac1_dat_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC1_LDACN(.O(DAC1_LDACn_pin), .I(dac1_ldacn_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC1_CLRN(.O(DAC1_CLRn_pin), .I(dac1_clrn_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC1_CSN(.O(DAC1_CSn_pin), .I(dac1_csn_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC2_DAT(.O(DAC2_DAT_pin), .I(dac2_dat_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC2_LDACN(.O(DAC2_LDACn_pin), .I(dac2_ldacn_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC2_CLRN(.O(DAC2_CLRn_pin), .I(dac2_clrn_o)); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_DAC2_CSN(.O(DAC2_CSn_pin), .I(dac2_csn_o)); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB0(.O(feedback[0]), .I(FB_pin[0])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB1(.O(feedback[1]), .I(FB_pin[1])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB2(.O(feedback[2]), .I(FB_pin[2])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB3(.O(feedback[3]), .I(FB_pin[3])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB4(.O(feedback[4]), .I(FB_pin[4])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB5(.O(feedback[5]), .I(FB_pin[5])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB6(.O(feedback[6]), .I(FB_pin[6])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB7(.O(feedback[7]), .I(FB_pin[7])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB8(.O(feedback[8]), .I(FB_pin[8])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB9(.O(feedback[9]), .I(FB_pin[9])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB10(.O(feedback[10]), .I(FB_pin[10])); IBUF #(.IBUF_LOW_PWR("TRUE"), .IOSTANDARD("DEFAULT")) IBUF_FB11(.O(feedback[11]), .I(FB_pin[11])); OBUF #(.DRIVE(12), .IOSTANDARD("DEFAULT"), .SLEW("SLOW")) OBUF_FB_CLK(.O(FB_CLK_pin), .I(CLK_usart)); wire CIe_RX_n_pin; wire [7:0] qcw_volume; wire gpio_io_mult; wire [63:0] gpio_io; wire [63:0] gpio2_o; wire [63:0] gpio2_i; //Design design_1_wrapper Block1( .DDR_0_addr(DDR_addr), .DDR_0_ba(DDR_ba), .DDR_0_cas_n(DDR_cas_n), .DDR_0_ck_n(DDR_ck_n), .DDR_0_ck_p(DDR_ck_p), .DDR_0_cke(DDR_cke), .DDR_0_cs_n(DDR_cs_n), .DDR_0_dm(DDR_dm), .DDR_0_dq(DDR_dq), .DDR_0_dqs_n(DDR_dqs_n), .DDR_0_dqs_p(DDR_dqs_p), .DDR_0_odt(DDR_odt), .DDR_0_ras_n(DDR_ras_n), .DDR_0_reset_n(DDR_reset_n), .DDR_0_we_n(DDR_we_n), .FCLK_CLK0_0(CLK_01), .FCLK_CLK1_0(CLK_o), .FCLK_CLK2_0(clk_m), .FCLK_CLK3_0(CLK_usart), .FIXED_IO_0_ddr_vrn(FIXED_IO_ddr_vrn), .FIXED_IO_0_ddr_vrp(FIXED_IO_ddr_vrp), .FIXED_IO_0_mio(MIO), .FIXED_IO_0_ps_clk(clk_i), .FIXED_IO_0_ps_porb(rst_i), .FIXED_IO_0_ps_srstb(rst_i), .GMII_ETHERNET_1_0_col(GMII_ETHERNET_1_col), .GMII_ETHERNET_1_0_crs(GMII_ETHERNET_1_cors), .GMII_ETHERNET_1_0_rx_clk(GMII_ETHERNET_1_rx_clk), .GMII_ETHERNET_1_0_rx_dv(GMII_ETHERNET_1_rx_dv), .GMII_ETHERNET_1_0_rx_er(GMII_ETHERNET_1_rx_er), .GMII_ETHERNET_1_0_rxd(ETH_RXd_pin), .GMII_ETHERNET_1_0_tx_clk(GMII_ETHERNET_1_tx_clk), .GMII_ETHERNET_1_0_tx_en(GMII_ETHERNET_1_tx_en), .GMII_ETHERNET_1_0_tx_er(GMII_ETHERNET_1_tx_er), .GMII_ETHERNET_1_0_txd(ETH_TXd_pin), .GPIO_I_0(gpio2_o), .GPIO_O_0(gpio2_i), .UART_0_0_rxd(UART_RX_deb), .UART_0_0_txd(UART_TX_deb), .UART_1_0_rxd(UART_RX_INT), .UART_1_0_txd(UART_TX_INT), .pci_exp_rxn_0(PCIe_RX_n), .pci_exp_rxp_0(PCIe_RX_p), .pci_exp_txn_0(PCIe_TX_n), .pci_exp_txp_0(PCIe_TX_p), .sys_clk_0(PCIe_CLK), .sys_rst_n_0(PCIe_RST_pin) ); assign gpio_io_mult = MIO[1]; pwr_controller Block2( .MCLK(mclk_i), .MDAT(mdat_i), .DAC_CLK(dac_clk_o), .DAC_DAT_1(dac1_dat_o), .DAC_CLRn_1(dac1_clrn_o), .DAC_LDACn_1(dac1_ldacn_o), .DAC_CSn_1(dac1_csn_o), .DAC_DAT_2(dac2_dat_o), .DAC_CLRn_2(dac2_clrn_o), .DAC_LDACn_2(dac2_ldacn_o), .DAC_CSn_2(dac2_csn_o), .CLK(CLK_o), .RST(rst_i), .vp_in(VP_pin), .vn_in(VN_pin), .pwr_on(pwr_on), .interrupter(interrupter), .TEMP_req(temp_req), .TEMP(temp), .TEMP_RDy(temp_RDy), .KvMETER1(KvMETER1) ); wire [17:0] volume; coil Block3( .CLK(CLK_01), .CLKm(clk_m), .RST(rst_i), .SIGNAL(audio_deamon), .FREQUEN(coil_freque_o), .FB(feedback), .VOL(audio_da_volume), .OUTA(outa_b), .OUTB(outb_b), .interrupter(interrupter), .pwr_on(pwr_on), .amplitude(qcw_volume) ); always @(posedge mclk_i) begin KvM1 <= KvMETER1; end protection Block4( .RST(rst_i), .CLK(mclk_i), .DATA(KvM1), .PROTECT(ovp_o) ); interrupter Block5( .CLK(CLK_usart), .RST(int), .DATA(spark), .sh(sh), .interrupt(interrupter) ); USART Block6( .CLK(CLK_usart), .RST(rst_i), .USART_Rx(USART_Rx), .USART_Tx(USART_Tx), .ERROR(err1), .T(TTemp1), .Kv(KvMETER2), .pwr_on(pwr_on), .qcw(qcw_on), .ovp(ovp_o), .DAC(outa_b) ); USART Block7( .CLK(CLK_usart), .RST(rst_i), .USART_Rx(USART2_Rx), .USART_Tx(USART2_Tx), .ERROR(err2), .T(TTemp2), .Kv(KvMETER3), .pwr_on(pwr_on), .qcw(qcw_on), .ovp(ovp_o), .DAC(outb_b) ); frequency_meter Block8 ( .RST(rst_i), .CLK(CLK_usart), .DAT(outa_b), .FREQ(freq_o) ); volume_control Block9 ( .RST(rst_i), .VOL(audio_da_volume), .VOL_Fr(volume) ); UART Block10 ( .CLK(CLK_uart), .RST(rst_i), .DAC1(outa_b), .DAC2(outb_b), .ON(pwr_on), .VOL(audio_da_volume), .UART_Tx(UART_TX_INT), .UART_Rx(UART_RX_INT) ); GPIO Block11 ( .pwr_on(pwr_on), .int(int), .qcw_on(qcw_on), .audio_deamon(audio_deamon), .qcw_volume(qcw_volume), .coil_freq(freq_o), .sh(sh), .spark(spark), .err1(err1), .err2(err2), .TTemp1(TTemp1), .TTemp2(TTemp2), .temp(temp), .freq_out(coil_freque_o), .gpio_o(gpio2_o), .gpio_i(gpio2_i) ); endmodule Изменено 3 мая пользователем makc Код убран под спойлер Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
andrew_b 15 2 мая Опубликовано 2 мая · Жалоба Во-первых, вы ошиблись подфорумом. Verilog не язык программирования. Вам сюда: https://electronix.ru/forum/forum/16-yazyki-proektirovaniya-na-plis-fpga/ Во-вторых, неужели вы думаете, что кто-то захочет разбирать вашу простыню кода, где нет ни единого комментария? 9 minutes ago, aliceLiddell said: Не работает даже синтез этих модулей совместно Какие ошибки выдаёт синтезатор? http://citforum.ru/howto/smart-questions-ru.shtml Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
aliceLiddell 0 2 мая Опубликовано 2 мая · Жалоба Спойлер *** Running vivado with args -log main.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source main.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source main.tcl -notrace create_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1334.379 ; gain = 25.832 ; free physical = 3976 ; free virtual = 29543 INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/mnt/1/Vivado/Vivado/2023.2/data/ip'. Command: read_checkpoint -auto_incremental -incremental /home/typo3/project_4/project_4.srcs/utils_1/imports/synth_1/main.dcp INFO: [Vivado 12-5825] Read reference checkpoint from /home/typo3/project_4/project_4.srcs/utils_1/imports/synth_1/main.dcp for incremental synthesis INFO: [Vivado 12-7989] Please ensure there are no constraint changes Command: synth_design -top main -part xc7z030ffg676-2 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z030' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z030' INFO: [Device 21-403] Loading part xc7z030ffg676-2 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 25238 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2144.188 ; gain = 408.684 ; free physical = 2844 ; free virtual = 28411 --------------------------------------------------------------------------------- INFO: [Synth 8-6157] synthesizing module 'main' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:23] INFO: [Synth 8-6157] synthesizing module 'BUFGCE_1' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1978] INFO: [Synth 8-6155] done synthesizing module 'BUFGCE_1' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1978] INFO: [Synth 8-6157] synthesizing module 'IBUF' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631] Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631] INFO: [Synth 8-6157] synthesizing module 'OBUF' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:93059] Parameter DRIVE bound to: 12 - type: integer Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-6155] done synthesizing module 'OBUF' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:93059] INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73646] Parameter DIFF_TERM bound to: FALSE - type: string Parameter IBUF_LOW_PWR bound to: TRUE - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73646] INFO: [Synth 8-6157] synthesizing module 'OBUFDS' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:93073] Parameter IOSTANDARD bound to: DEFAULT - type: string Parameter SLEW bound to: FAST - type: string INFO: [Synth 8-6155] done synthesizing module 'OBUFDS' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:93073] INFO: [Synth 8-6157] synthesizing module 'design_1_wrapper' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] INFO: [Synth 8-6157] synthesizing module 'design_1' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:13] INFO: [Synth 8-6157] synthesizing module 'design_1_axi_fifo_mm_s_2' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_axi_fifo_mm_s_2_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_axi_fifo_mm_s_2' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_axi_fifo_mm_s_2_stub.v:6] WARNING: [Synth 8-7071] port 'interrupt' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7071] port 'mm2s_prmry_reset_out_n' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7071] port 'mm2s_cntrl_reset_out_n' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7071] port 'axi_str_txc_tvalid' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7071] port 'axi_str_txc_tlast' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7071] port 'axi_str_txc_tdata' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7071] port 's2mm_prmry_reset_out_n' of module 'design_1_axi_fifo_mm_s_2' is unconnected for instance 'axi_fifo_mm_s' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] WARNING: [Synth 8-7023] instance 'axi_fifo_mm_s' of module 'design_1_axi_fifo_mm_s_2' has 35 connections declared, but only 28 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:301] INFO: [Synth 8-6157] synthesizing module 'design_1_axis_dwidth_converter_3' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_axis_dwidth_converter_3_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_axis_dwidth_converter_3' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_axis_dwidth_converter_3_stub.v:6] WARNING: [Synth 8-7071] port 'm_axis_tkeep' of module 'design_1_axis_dwidth_converter_3' is unconnected for instance 'axis_dwidth_converter' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:330] WARNING: [Synth 8-7023] instance 'axis_dwidth_converter' of module 'design_1_axis_dwidth_converter_3' has 12 connections declared, but only 11 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:330] INFO: [Synth 8-6157] synthesizing module 'design_1_axis_subset_converter_1' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_axis_subset_converter_1_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_axis_subset_converter_1' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_axis_subset_converter_1_stub.v:6] INFO: [Synth 8-6157] synthesizing module 'design_1_pcie_7x_0_1' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_pcie_7x_0_1_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_pcie_7x_0_1' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_pcie_7x_0_1_stub.v:6] WARNING: [Synth 8-7071] port 'pipe_txoutclk_out' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pipe_rxoutclk_out' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pipe_pclk_sel_out' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pipe_gen3_out' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'user_lnk_up' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'user_app_rdy' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'tx_buf_av' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'tx_cfg_req' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'tx_err_drop' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'm_axis_rx_tuser' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'fc_cpld' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'fc_cplh' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'fc_npd' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'fc_nph' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'fc_pd' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'fc_ph' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_mgmt_do' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_mgmt_rd_wr_done' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_status' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_command' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_dstatus' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_dcommand' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_lstatus' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_lcommand' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_dcommand2' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_pcie_link_state' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_pmcsr_pme_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_pmcsr_powerstate' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_pmcsr_pme_status' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_received_func_lvl_rst' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_err_cpl_rdy' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_interrupt_rdy' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_interrupt_do' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_interrupt_mmenable' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_interrupt_msienable' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_interrupt_msixenable' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_interrupt_msixfm' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_to_turnoff' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_bus_number' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_device_number' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_function_number' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_data' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_bridge_serr_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_slot_control_electromech_il_ctl_pulse' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_root_control_syserr_corr_err_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_root_control_syserr_non_fatal_err_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_root_control_syserr_fatal_err_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_root_control_pme_int_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_rooterr_corr_err_reporting_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_rooterr_non_fatal_err_reporting_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_rooterr_fatal_err_reporting_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_rooterr_corr_err_received' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_rooterr_non_fatal_err_received' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_rooterr_fatal_err_received' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_err_cor' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_err_non_fatal' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_err_fatal' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_pm_as_nak' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_pm_pme' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_pme_to_ack' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_assert_int_a' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_assert_int_b' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_assert_int_c' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_assert_int_d' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_deassert_int_a' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_deassert_int_b' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_deassert_int_c' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_deassert_int_d' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_msg_received_setslotpowerlimit' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_sel_lnk_rate' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_sel_lnk_width' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_ltssm_state' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_lane_reversal_mode' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_phy_lnk_up' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_tx_pm_state' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_rx_pm_state' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_link_upcfg_cap' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_link_gen2_cap' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_link_partner_gen2_supported' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_initial_link_width' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_directed_change_done' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pl_received_hot_rst' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_err_aer_headerlog_set' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_ecrc_check_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_aer_ecrc_gen_en' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'cfg_vc_tcvc_map' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pcie_drp_do' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7071] port 'pcie_drp_rdy' of module 'design_1_pcie_7x_0_1' is unconnected for instance 'pcie_7x_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] WARNING: [Synth 8-7023] instance 'pcie_7x_0' of module 'design_1_pcie_7x_0_1' has 176 connections declared, but only 87 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:353] INFO: [Synth 8-6157] synthesizing module 'design_1_processing_system7_0_1' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_processing_system7_0_1_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_processing_system7_0_1' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_processing_system7_0_1_stub.v:6] WARNING: [Synth 8-7071] port 'GPIO_T' of module 'design_1_processing_system7_0_1' is unconnected for instance 'processing_system7_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:441] WARNING: [Synth 8-7071] port 'FCLK_RESET0_N' of module 'design_1_processing_system7_0_1' is unconnected for instance 'processing_system7_0' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:441] WARNING: [Synth 8-7023] instance 'processing_system7_0' of module 'design_1_processing_system7_0_1' has 122 connections declared, but only 120 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:441] INFO: [Synth 8-6157] synthesizing module 'design_1_ps7_0_axi_periph_2' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1099] INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_UYSKKA' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1683] INFO: [Synth 8-6157] synthesizing module 'design_1_auto_pc_0' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_auto_pc_0_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_auto_pc_0' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_auto_pc_0_stub.v:6] WARNING: [Synth 8-7071] port 'm_axi_awprot' of module 'design_1_auto_pc_0' is unconnected for instance 'auto_pc' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1918] INFO: [Common 17-14] Message 'Synth 8-7071' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Synth 8-7023] instance 'auto_pc' of module 'design_1_auto_pc_0' has 59 connections declared, but only 57 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1918] INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_UYSKKA' (0#1) [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1683] INFO: [Synth 8-6155] done synthesizing module 'design_1_ps7_0_axi_periph_2' (0#1) [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1099] INFO: [Synth 8-6157] synthesizing module 'design_1_ps7_0_axi_periph_1_2' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:689] INFO: [Synth 8-6157] synthesizing module 's00_couplers_imp_7URNSC' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1404] INFO: [Synth 8-6155] done synthesizing module 's00_couplers_imp_7URNSC' (0#1) [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:1404] INFO: [Synth 8-6155] done synthesizing module 'design_1_ps7_0_axi_periph_1_2' (0#1) [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:689] WARNING: [Synth 8-7023] instance 'ps7_0_axi_periph_1' of module 'design_1_ps7_0_axi_periph_1_2' has 82 connections declared, but only 55 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:624] INFO: [Synth 8-6157] synthesizing module 'design_1_rst_pcie_7x_0_62M_2' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_rst_pcie_7x_0_62M_2_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'design_1_rst_pcie_7x_0_62M_2' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/design_1_rst_pcie_7x_0_62M_2_stub.v:6] WARNING: [Synth 8-7023] instance 'rst_pcie_7x_0_62M' of module 'design_1_rst_pcie_7x_0_62M_2' has 10 connections declared, but only 6 given [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:680] INFO: [Synth 8-6155] done synthesizing module 'design_1' (0#1) [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:13] INFO: [Synth 8-6155] done synthesizing module 'design_1_wrapper' (0#1) [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v:13] WARNING: [Synth 8-689] width (16) of port connection 'DDR_0_addr' does not match port width (15) of module 'design_1_wrapper' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:293] WARNING: [Synth 8-6104] Input port 'DDR_dm' has an internal driver [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:300] WARNING: [Synth 8-7023] instance 'Block1' of module 'design_1_wrapper' has 48 connections declared, but only 47 given [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:292] INFO: [Synth 8-6157] synthesizing module 'pwr_controller' [/home/typo3/project_4/project_4.srcs/sources_1/new/pwr_controller.v:23] INFO: [Synth 8-6157] synthesizing module 'TRC' [/home/typo3/project_4/project_4.srcs/sources_1/new/TRC.v:21] INFO: [Synth 8-6157] synthesizing module 'CR_' [/home/typo3/project_4/project_4.srcs/sources_1/new/CR.v:21] INFO: [Synth 8-6157] synthesizing module 'FDCE' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40789] Parameter INIT bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'FDCE' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:40789] INFO: [Synth 8-6155] done synthesizing module 'CR_' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/CR.v:21] WARNING: [Synth 8-7023] instance 'trc' of module 'CR_' has 5 connections declared, but only 4 given [/home/typo3/project_4/project_4.srcs/sources_1/new/TRC.v:32] INFO: [Synth 8-6155] done synthesizing module 'TRC' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/TRC.v:21] INFO: [Synth 8-6157] synthesizing module 'xadc_design' [/home/typo3/project_4/project_4.srcs/sources_1/new/xadc_design.v:23] INFO: [Synth 8-6157] synthesizing module 'xadc_wiz_0' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/xadc_wiz_0_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'xadc_wiz_0' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/xadc_wiz_0_stub.v:6] WARNING: [Synth 8-7023] instance 'XADC2' of module 'xadc_wiz_0' has 23 connections declared, but only 16 given [/home/typo3/project_4/project_4.srcs/sources_1/new/xadc_design.v:59] INFO: [Synth 8-6155] done synthesizing module 'xadc_design' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/xadc_design.v:23] INFO: [Synth 8-6157] synthesizing module 'vco' [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:23] INFO: [Synth 8-6157] synthesizing module 'sum' [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:21] INFO: [Synth 8-6155] done synthesizing module 'sum' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:21] WARNING: [Synth 8-689] width (48) of port connection 'Q' does not match port width (49) of module 'sum' [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:64] INFO: [Synth 8-6157] synthesizing module 'sub' [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:34] INFO: [Synth 8-6155] done synthesizing module 'sub' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:34] WARNING: [Synth 8-689] width (48) of port connection 'Q' does not match port width (49) of module 'sub' [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:65] INFO: [Synth 8-6157] synthesizing module 'RC' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/RC.v:21] WARNING: [Synth 8-567] referenced signal 'negat' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/RC.v:45] WARNING: [Synth 8-567] referenced signal 'posit' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/RC.v:45] INFO: [Synth 8-6155] done synthesizing module 'RC' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/RC.v:21] INFO: [Synth 8-6157] synthesizing module 'cordic_0' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_0_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'cordic_0' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_0_stub.v:6] WARNING: [Synth 8-689] width (13) of port connection 'm_axis_dout_tdata' does not match port width (32) of module 'cordic_0' [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:75] WARNING: [Synth 8-7023] instance 'cd' of module 'cordic_0' has 7 connections declared, but only 6 given [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:71] INFO: [Synth 8-6155] done synthesizing module 'vco' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:23] INFO: [Synth 8-6157] synthesizing module 'DAC_in' [/home/typo3/project_4/project_4.srcs/sources_1/new/DAC_in.v:23] WARNING: [Synth 8-324] index 6 out of range [/home/typo3/project_4/project_4.srcs/sources_1/new/DAC_in.v:91] INFO: [Synth 8-6157] synthesizing module 'DCM' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:31765] Parameter DFS_FREQUENCY_MODE bound to: HIGH - type: string Parameter DLL_FREQUENCY_MODE bound to: HIGH - type: string INFO: [Synth 8-6155] done synthesizing module 'DCM' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:31765] WARNING: [Synth 8-7023] instance 'DCM_inst' of module 'DCM' has 19 connections declared, but only 3 given [/home/typo3/project_4/project_4.srcs/sources_1/new/DAC_in.v:46] INFO: [Synth 8-6155] done synthesizing module 'DAC_in' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/DAC_in.v:23] WARNING: [Synth 8-689] width (13) of port connection 'ina' does not match port width (12) of module 'DAC_in' [/home/typo3/project_4/project_4.srcs/sources_1/new/pwr_controller.v:153] WARNING: [Synth 8-689] width (13) of port connection 'inb' does not match port width (12) of module 'DAC_in' [/home/typo3/project_4/project_4.srcs/sources_1/new/pwr_controller.v:155] INFO: [Synth 8-6155] done synthesizing module 'pwr_controller' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/pwr_controller.v:23] INFO: [Synth 8-6157] synthesizing module 'coil' [/home/typo3/project_4/project_4.srcs/sources_1/new/coil.v:23] INFO: [Synth 8-6157] synthesizing module 'R10' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/R10.v:21] INFO: [Synth 8-6157] synthesizing module 'latch' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/latch.v:21] INFO: [Synth 8-6157] synthesizing module 'FDRE' [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005] Parameter INIT bound to: 1'b0 INFO: [Synth 8-6155] done synthesizing module 'FDRE' (0#1) [/mnt/1/Vivado/Vivado/2023.2/scripts/rt/data/unisim_comp.v:41005] INFO: [Synth 8-6155] done synthesizing module 'latch' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/latch.v:21] INFO: [Synth 8-6155] done synthesizing module 'R10' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/R10.v:21] INFO: [Synth 8-6157] synthesizing module 'action1024' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action1024.v:21] INFO: [Synth 8-6157] synthesizing module 'cordic_1' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_1_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'cordic_1' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_1_stub.v:6] WARNING: [Synth 8-689] width (30) of port connection 'm_axis_dout_tdata' does not match port width (24) of module 'cordic_1' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action1024.v:39] INFO: [Synth 8-6157] synthesizing module 'cordic_2' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_2_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'cordic_2' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_2_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'action1024' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action1024.v:21] INFO: [Synth 8-6157] synthesizing module 'R16' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/R12.v:21] INFO: [Synth 8-6155] done synthesizing module 'R16' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/R12.v:21] INFO: [Synth 8-6157] synthesizing module 'action65536' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action4096.v:21] INFO: [Synth 8-6157] synthesizing module 'cordic_3' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_3_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'cordic_3' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_3_stub.v:6] WARNING: [Synth 8-689] width (30) of port connection 'm_axis_dout_tdata' does not match port width (32) of module 'cordic_3' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action4096.v:38] INFO: [Synth 8-6157] synthesizing module 'cordic_4' [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_4_stub.v:6] INFO: [Synth 8-6155] done synthesizing module 'cordic_4' (0#1) [/home/typo3/project_4/project_4.runs/synth_1/.Xil/Vivado-25202-localhost.localdomain/realtime/cordic_4_stub.v:6] WARNING: [Synth 8-689] width (48) of port connection 'm_axis_dout_tdata' does not match port width (32) of module 'cordic_4' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action4096.v:48] INFO: [Synth 8-6155] done synthesizing module 'action65536' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/action4096.v:21] WARNING: [Synth 8-7023] instance 'A3' of module 'action65536' has 5 connections declared, but only 4 given [/home/typo3/project_4/project_4.srcs/sources_1/new/coil.v:116] WARNING: [Synth 8-7023] instance 'A4' of module 'action65536' has 5 connections declared, but only 4 given [/home/typo3/project_4/project_4.srcs/sources_1/new/coil.v:125] INFO: [Synth 8-6157] synthesizing module 'mult28x18' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/mult28x18.v:21] INFO: [Synth 8-6155] done synthesizing module 'mult28x18' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/mult28x18.v:21] INFO: [Synth 8-6157] synthesizing module 'mult28x47' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/mult28x18.v:30] INFO: [Synth 8-6155] done synthesizing module 'mult28x47' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/mult28x18.v:30] INFO: [Synth 8-6155] done synthesizing module 'coil' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/coil.v:23] WARNING: [Synth 8-689] width (13) of port connection 'SIGNAL' does not match port width (12) of module 'coil' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:374] INFO: [Synth 8-6157] synthesizing module 'protection' [/home/typo3/project_4/project_4.srcs/sources_1/new/protection.v:23] INFO: [Synth 8-6155] done synthesizing module 'protection' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/protection.v:23] INFO: [Synth 8-6157] synthesizing module 'interrupter' [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:23] INFO: [Synth 8-6157] synthesizing module 'latch2' [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/latch.v:31] INFO: [Synth 8-6155] done synthesizing module 'latch2' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/lib/latch.v:31] WARNING: [Synth 8-567] referenced signal 'clr1' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:96] WARNING: [Synth 8-567] referenced signal 'clr2' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:96] INFO: [Synth 8-6155] done synthesizing module 'interrupter' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:23] WARNING: [Synth 8-689] width (32) of port connection 'DATA' does not match port width (13) of module 'interrupter' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:400] INFO: [Synth 8-6157] synthesizing module 'USART' [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:23] WARNING: [Synth 8-567] referenced signal 'Tx' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:47] WARNING: [Synth 8-567] referenced signal 'CNT1' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:47] WARNING: [Synth 8-567] referenced signal 'pwr_on' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:47] WARNING: [Synth 8-567] referenced signal 'DAC' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:47] WARNING: [Synth 8-567] referenced signal 'qcw' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:47] INFO: [Synth 8-6155] done synthesizing module 'USART' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/USART.v:23] INFO: [Synth 8-6157] synthesizing module 'frequency_meter' [/home/typo3/project_4/project_4.srcs/sources_1/new/frequency_meter.v:23] WARNING: [Synth 8-689] width (10) of port connection 'Q' does not match port width (12) of module 'R10' [/home/typo3/project_4/project_4.srcs/sources_1/new/frequency_meter.v:37] INFO: [Synth 8-6155] done synthesizing module 'frequency_meter' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/frequency_meter.v:23] INFO: [Synth 8-6157] synthesizing module 'volume_control' [/home/typo3/project_4/project_4.srcs/sources_1/new/volume_control.v:23] INFO: [Synth 8-6155] done synthesizing module 'volume_control' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/volume_control.v:23] WARNING: [Synth 8-689] width (8) of port connection 'VOL' does not match port width (7) of module 'volume_control' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:445] WARNING: [Synth 8-7023] instance 'Block9' of module 'volume_control' has 4 connections declared, but only 3 given [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:442] INFO: [Synth 8-6157] synthesizing module 'UART' [/home/typo3/project_4/project_4.srcs/sources_1/new/UART.v:23] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/home/typo3/project_4/project_4.srcs/sources_1/new/uart_rx.v:32] INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/uart_rx.v:32] WARNING: [Synth 8-7023] instance 'nolabel_line64' of module 'uart_rx' has 10 connections declared, but only 7 given [/home/typo3/project_4/project_4.srcs/sources_1/new/UART.v:64] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/home/typo3/project_4/project_4.srcs/sources_1/new/uart_tx.v:32] INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/uart_tx.v:32] WARNING: [Synth 8-7023] instance 'nolabel_line127' of module 'uart_tx' has 8 connections declared, but only 7 given [/home/typo3/project_4/project_4.srcs/sources_1/new/UART.v:127] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/UART.v:23] INFO: [Synth 8-6157] synthesizing module 'GPIO' [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:23] WARNING: [Synth 8-567] referenced signal 'tx' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'err1' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'err2' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'TTemp1' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'TTemp2' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'temp' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'freq_out' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] WARNING: [Synth 8-567] referenced signal 'txD' should be on the sensitivity list [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:121] INFO: [Synth 8-6155] done synthesizing module 'GPIO' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:23] WARNING: [Synth 8-689] width (13) of port connection 'audio_deamon' does not match port width (12) of module 'GPIO' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:466] WARNING: [Synth 8-689] width (32) of port connection 'spark' does not match port width (8) of module 'GPIO' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:470] WARNING: [Synth 8-7023] instance 'Block11' of module 'GPIO' has 18 connections declared, but only 16 given [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:461] INFO: [Synth 8-6155] done synthesizing module 'main' (0#1) [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:23] WARNING: [Synth 8-3848] Net write in module/entity xadc_design does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/xadc_design.v:43] WARNING: [Synth 8-3848] Net int_intr_flag in module/entity vco does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/vco.v:48] WARNING: [Synth 8-3848] Net clk_o in module/entity DAC_in does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/DAC_in.v:30] WARNING: [Synth 8-3848] Net OUTB in module/entity coil does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/coil.v:32] WARNING: [Synth 8-3848] Net down in module/entity interrupter does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:85] WARNING: [Synth 8-6014] Unused sequential element CMD_reg was removed. [/home/typo3/project_4/project_4.srcs/sources_1/new/UART.v:53] WARNING: [Synth 8-3848] Net VOLfl in module/entity UART does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/UART.v:48] WARNING: [Synth 8-3848] Net gpio_o in module/entity GPIO does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:42] WARNING: [Synth 8-3848] Net tx in module/entity GPIO does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:49] WARNING: [Synth 8-3848] Net sh in module/entity GPIO does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:30] WARNING: [Synth 8-3848] Net tx in module/entity GPIO does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:49] WARNING: [Synth 8-3848] Net CLK_deb_pin in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:28] WARNING: [Synth 8-3848] Net PCIe_RST_pin in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:50] WARNING: [Synth 8-3848] Net PCIe_CLK_pin in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:51] WARNING: [Synth 8-3848] Net eth_rx_err_pin in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:85] WARNING: [Synth 8-3848] Net GMII_ETHERNET_1_col in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:112] WARNING: [Synth 8-3848] Net GMII_ETHERNET_1_cors in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:113] WARNING: [Synth 8-3848] Net GMII_ETHERNET_1_rx_er in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:116] WARNING: [Synth 8-3848] Net UART_RX_INT in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:187] WARNING: [Synth 8-3848] Net PCIe_CLK in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:169] WARNING: [Synth 8-3848] Net coil_freque_o in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:139] WARNING: [Synth 8-3848] Net temp_req in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:131] WARNING: [Synth 8-3848] Net CLK_uart in module/entity main does not have driver. [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:185] WARNING: [Synth 8-3917] design main has port DDR_addr[15] driven by constant 0 WARNING: [Synth 8-7129] Port sh in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[63] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[61] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[60] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[59] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[58] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[57] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[56] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[55] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[54] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[53] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[52] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[51] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[50] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[49] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[48] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[47] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[46] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[45] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[44] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[43] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[42] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[41] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[40] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[39] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[38] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[37] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[36] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[35] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[34] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[33] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[32] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[31] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_o[30] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[62] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[61] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[60] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[30] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[29] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[28] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[27] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[26] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[25] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[24] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[23] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[22] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[21] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[20] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[19] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[18] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[17] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[16] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[15] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[14] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[13] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[12] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[11] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[10] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[9] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[8] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[7] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[6] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[5] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[4] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[3] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[2] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[1] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port gpio_i[0] in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port rst in module GPIO is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[4] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[3] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[2] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC1[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[11] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[10] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[9] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[8] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[7] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[6] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[5] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[4] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[3] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[2] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[1] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port DAC2[0] in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port ON in module UART is either unconnected or has no load WARNING: [Synth 8-7129] Port RST in module action1024 is either unconnected or has no load WARNING: [Synth 8-7129] Port RST in module USART is either unconnected or has no load WARNING: [Synth 8-7129] Port USART_Rx in module USART is either unconnected or has no load WARNING: [Synth 8-7129] Port ovp in module USART is either unconnected or has no load WARNING: [Synth 8-7129] Port RST in module interrupter is either unconnected or has no load WARNING: [Synth 8-7129] Port OUTB in module coil is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2244.125 ; gain = 508.621 ; free physical = 2742 ; free virtual = 28309 --------------------------------------------------------------------------------- Warning: net DDR_dm has 1 drive pin and 1 bidir pins Warning: net clk_i has 1 drive pin and 1 bidir pins CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin GMII_ETHERNET_1_tx_en with 1st driver pin 'IBUF_ETH_TEN/O' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:209] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin GMII_ETHERNET_1_tx_en with 2nd driver pin 'Block1/design_1_i/processing_system7_0/ENET1_GMII_TX_EN[0]' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:441] Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 1|Failed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2256.000 ; gain = 520.496 ; free physical = 2734 ; free virtual = 28301 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2256.000 ; gain = 520.496 ; free physical = 2734 ; free virtual = 28301 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2261.938 ; gain = 0.000 ; free physical = 2727 ; free virtual = 28295 INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement WARNING: [Netlist 29-365] DCM_ADV instance 'Block2/DAC/DCM_inst' has been transformed into an MMCM. Please check the output clock waveforms for correctness. If the output clocks are incorrect, modify your design to use the MMCME<#>_ADV native to the target architecture. WARNING: [Netlist 29-365] DCM_ADV instance 'Block2/DAC/DCM_inst' has been transformed into an MMCM. Please check the output clock waveforms for correctness. If the output clocks are incorrect, modify your design to use the MMCME<#>_ADV native to the target architecture. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc] for cell 'Block1/design_1_i/processing_system7_0' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc] for cell 'Block1/design_1_i/processing_system7_0' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_pcie_7x_0_1/design_1_pcie_7x_0_1/design_1_pcie_7x_0_1_in_context.xdc] for cell 'Block1/design_1_i/pcie_7x_0' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_pcie_7x_0_1/design_1_pcie_7x_0_1/design_1_pcie_7x_0_1_in_context.xdc] for cell 'Block1/design_1_i/pcie_7x_0' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_2/design_1_axi_fifo_mm_s_2/design_1_axi_fifo_mm_s_2_in_context.xdc] for cell 'Block1/design_1_i/axi_fifo_mm_s' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_axi_fifo_mm_s_2/design_1_axi_fifo_mm_s_2/design_1_axi_fifo_mm_s_2_in_context.xdc] for cell 'Block1/design_1_i/axi_fifo_mm_s' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_rst_pcie_7x_0_62M_2/design_1_rst_pcie_7x_0_62M_2/design_1_rst_pcie_7x_0_62M_2_in_context.xdc] for cell 'Block1/design_1_i/rst_pcie_7x_0_62M' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_rst_pcie_7x_0_62M_2/design_1_rst_pcie_7x_0_62M_2/design_1_rst_pcie_7x_0_62M_2_in_context.xdc] for cell 'Block1/design_1_i/rst_pcie_7x_0_62M' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0/design_1_auto_pc_0_in_context.xdc] for cell 'Block1/design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_auto_pc_0/design_1_auto_pc_0/design_1_auto_pc_0_in_context.xdc] for cell 'Block1/design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_axis_subset_converter_1/design_1_axis_subset_converter_1/design_1_axis_subset_converter_1_in_context.xdc] for cell 'Block1/design_1_i/axis_subset_converter' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_axis_subset_converter_1/design_1_axis_subset_converter_1/design_1_axis_subset_converter_1_in_context.xdc] for cell 'Block1/design_1_i/axis_subset_converter' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_axis_dwidth_converter_3/design_1_axis_dwidth_converter_3/design_1_axis_dwidth_converter_3_in_context.xdc] for cell 'Block1/design_1_i/axis_dwidth_converter' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_axis_dwidth_converter_3/design_1_axis_dwidth_converter_3/design_1_axis_dwidth_converter_3_in_context.xdc] for cell 'Block1/design_1_i/axis_dwidth_converter' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/xadc_wiz_0/xadc_wiz_0/xadc_wiz_0_in_context.xdc] for cell 'Block2/nolabel_line120/XADC2' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/xadc_wiz_0/xadc_wiz_0/xadc_wiz_0_in_context.xdc] for cell 'Block2/nolabel_line120/XADC2' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block3/A1/S1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block3/A1/S1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block3/A2/S1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block3/A2/S1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block8/A1/S1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block8/A1/S1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block8/A2/S1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_1/cordic_1/cordic_1_in_context.xdc] for cell 'Block8/A2/S1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_3/cordic_3/cordic_3_in_context.xdc] for cell 'Block3/A3/S1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_3/cordic_3/cordic_3_in_context.xdc] for cell 'Block3/A3/S1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_3/cordic_3/cordic_3_in_context.xdc] for cell 'Block3/A4/S1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_3/cordic_3/cordic_3_in_context.xdc] for cell 'Block3/A4/S1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_4/cordic_4/cordic_4_in_context.xdc] for cell 'Block3/A3/A1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_4/cordic_4/cordic_4_in_context.xdc] for cell 'Block3/A3/A1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_4/cordic_4/cordic_4_in_context.xdc] for cell 'Block3/A4/A1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_4/cordic_4/cordic_4_in_context.xdc] for cell 'Block3/A4/A1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_0/cordic_0/cordic_0_in_context.xdc] for cell 'Block2/nolabel_line134/cd' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_0/cordic_0/cordic_0_in_context.xdc] for cell 'Block2/nolabel_line134/cd' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_0/cordic_0/cordic_0_in_context.xdc] for cell 'Block3/nolabel_line156/cd' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_0/cordic_0/cordic_0_in_context.xdc] for cell 'Block3/nolabel_line156/cd' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block3/A1/A1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block3/A1/A1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block3/A2/A1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block3/A2/A1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block8/A1/A1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block8/A1/A1' Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block8/A2/A1' Finished Parsing XDC File [/home/typo3/project_4/project_4.gen/sources_1/ip/cordic_2/cordic_2/cordic_2_in_context.xdc] for cell 'Block8/A2/A1' Parsing XDC File [/home/typo3/project_4/project_4.runs/synth_1/dont_touch.xdc] Finished Parsing XDC File [/home/typo3/project_4/project_4.runs/synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2368.734 ; gain = 0.000 ; free physical = 2710 ; free virtual = 28280 INFO: [Project 1-111] Unisim Transformation Summary: A total of 4 instances were transformed. BUFGCE_1 => BUFGCTRL: 1 instance DCM => MMCME2_ADV: 1 instance OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS(x2)): 2 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2368.770 ; gain = 0.000 ; free physical = 2710 ; free virtual = 28280 WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A1/A1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A1/S1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A2/A1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A2/S1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A3/A1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A3/S1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A4/A1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block3/A4/S1' at clock pin 'aclk' is different from the actual clock period '11.666', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block8/A1/A1' at clock pin 'aclk' is different from the actual clock period '45.555', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block8/A1/S1' at clock pin 'aclk' is different from the actual clock period '45.555', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block8/A2/A1' at clock pin 'aclk' is different from the actual clock period '45.555', this can lead to different synthesis results. WARNING: [Timing 38-316] Clock period '1000.000' specified during out-of-context synthesis of instance 'Block8/A2/S1' at clock pin 'aclk' is different from the actual clock period '45.555', this can lead to different synthesis results. INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2704 ; free virtual = 28272 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z030ffg676-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2704 ; free virtual = 28272 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 51). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 52). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 59). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 60). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 67). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 68). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 75). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 76). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 97). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 98). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 119). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 120). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 125). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 126). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 127). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 128). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 129). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 130). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 131). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 132). Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 133). Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/typo3/project_4/project_4.gen/sources_1/bd/design_1/ip/design_1_processing_system7_0_1/design_1_processing_system7_0_1/design_1_processing_system7_0_1_in_context.xdc, line 134). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/processing_system7_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/pcie_7x_0. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/axi_fifo_mm_s. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/rst_pcie_7x_0_62M. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/ps7_0_axi_periph/s00_couplers/auto_pc. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/ps7_0_axi_periph. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/axis_subset_converter. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/axis_dwidth_converter. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block1/design_1_i/ps7_0_axi_periph_1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block2/nolabel_line120/XADC2. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A1/S1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A2/S1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block8/A1/S1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block8/A2/S1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A3/S1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A4/S1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A3/A1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A4/A1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block2/nolabel_line134/cd. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/nolabel_line156/cd. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A1/A1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block3/A2/A1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block8/A1/A1. (constraint file auto generated constraint). Applied set_property KEEP_HIERARCHY = SOFT for Block8/A2/A1. (constraint file auto generated constraint). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2704 ; free virtual = 28272 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'count_rx_to3_reg' in module 'GPIO' INFO: [Synth 8-802] inferred FSM for state register 'count_tx_to2_reg' in module 'GPIO' WARNING: [Synth 8-327] inferring latch for variable 'stop_reg' [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:88] WARNING: [Synth 8-327] inferring latch for variable 'plasm1_reg' [/home/typo3/project_4/project_4.srcs/sources_1/new/interrupter.v:78] WARNING: [Synth 8-327] inferring latch for variable 'gpio_reg_reg' [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:102] WARNING: [Synth 8-327] inferring latch for variable 'txD_reg' [/home/typo3/project_4/project_4.srcs/sources_1/new/GPIO.v:126] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2702 ; free virtual = 28272 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 49 Bit Adders := 2 3 Input 49 Bit Adders := 2 7 Input 48 Bit Adders := 1 3 Input 48 Bit Adders := 1 2 Input 19 Bit Adders := 3 2 Input 6 Bit Adders := 1 2 Input 4 Bit Adders := 2 +---Registers : 49 Bit Registers := 4 25 Bit Registers := 2 18 Bit Registers := 2 16 Bit Registers := 2 13 Bit Registers := 5 12 Bit Registers := 5 9 Bit Registers := 1 8 Bit Registers := 8 7 Bit Registers := 1 6 Bit Registers := 1 4 Bit Registers := 2 1 Bit Registers := 36 +---Multipliers : 29x48 Multipliers := 4 +---Muxes : 2 Input 52 Bit Muxes := 1 2 Input 19 Bit Muxes := 1 3 Input 19 Bit Muxes := 1 2 Input 15 Bit Muxes := 2 2 Input 12 Bit Muxes := 4 2 Input 11 Bit Muxes := 2 2 Input 9 Bit Muxes := 2 3 Input 7 Bit Muxes := 1 4 Input 4 Bit Muxes := 2 2 Input 4 Bit Muxes := 4 2 Input 3 Bit Muxes := 2 2 Input 1 Bit Muxes := 65 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 400 (col length:80) BRAMs: 530 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met WARNING: [Synth 8-3936] Found unconnected internal register 'nolabel_line134/S2/Q_reg' and it is trimmed from '49' to '48' bits. [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:43] WARNING: [Synth 8-3936] Found unconnected internal register 'nolabel_line134/S1/Q_reg' and it is trimmed from '49' to '48' bits. [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:30] WARNING: [Synth 8-3936] Found unconnected internal register 'S2/Q_reg' and it is trimmed from '49' to '48' bits. [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:43] WARNING: [Synth 8-3936] Found unconnected internal register 'S1/Q_reg' and it is trimmed from '49' to '48' bits. [/home/typo3/project_4/project_4.srcs/sources_1/new/sum.v:30] DSP Report: Generating DSP A1/s_axis_cartesian_tdata0, operation Mode is: (C:0x1)-A*B. DSP Report: operator A1/s_axis_cartesian_tdata0 is absorbed into DSP A1/s_axis_cartesian_tdata0. DSP Report: operator A1/s_axis_cartesian_tdata1 is absorbed into DSP A1/s_axis_cartesian_tdata0. DSP Report: Generating DSP A2/s_axis_cartesian_tdata0, operation Mode is: (C:0x1)-A*B. DSP Report: operator A2/s_axis_cartesian_tdata0 is absorbed into DSP A2/s_axis_cartesian_tdata0. DSP Report: operator A2/s_axis_cartesian_tdata1 is absorbed into DSP A2/s_axis_cartesian_tdata0. DSP Report: Generating DSP A3/s_axis_cartesian_tdata0, operation Mode is: (C:0x1)-A*B. DSP Report: operator A3/s_axis_cartesian_tdata0 is absorbed into DSP A3/s_axis_cartesian_tdata0. DSP Report: operator A3/s_axis_cartesian_tdata1 is absorbed into DSP A3/s_axis_cartesian_tdata0. DSP Report: Generating DSP A4/s_axis_cartesian_tdata0, operation Mode is: (C:0x1)-A*B. DSP Report: operator A4/s_axis_cartesian_tdata0 is absorbed into DSP A4/s_axis_cartesian_tdata0. DSP Report: operator A4/s_axis_cartesian_tdata1 is absorbed into DSP A4/s_axis_cartesian_tdata0. DSP Report: Generating DSP OUTA1, operation Mode is: A*B. DSP Report: operator OUTA1 is absorbed into DSP OUTA1. DSP Report: Generating DSP A1/s_axis_cartesian_tdata0, operation Mode is: (C:0x1)-A*B. DSP Report: operator A1/s_axis_cartesian_tdata0 is absorbed into DSP A1/s_axis_cartesian_tdata0. DSP Report: operator A1/s_axis_cartesian_tdata1 is absorbed into DSP A1/s_axis_cartesian_tdata0. DSP Report: Generating DSP A2/s_axis_cartesian_tdata0, operation Mode is: (C:0x1)-A*B. DSP Report: operator A2/s_axis_cartesian_tdata0 is absorbed into DSP A2/s_axis_cartesian_tdata0. DSP Report: operator A2/s_axis_cartesian_tdata1 is absorbed into DSP A2/s_axis_cartesian_tdata0. WARNING: [Synth 8-3917] design main has port DDR_addr[15] driven by constant 0 WARNING: [Synth 8-3332] Sequential element (T1[0].RC/trc/RS1) is unused and will be removed from module pwr_controller. WARNING: [Synth 8-3332] Sequential element (T1[1].RC/trc/RS1) is unused and will be removed from module pwr_controller. WARNING: [Synth 8-3332] Sequential element (T1[2].RC/trc/RS1) is unused and will be removed from module pwr_controller. WARNING: [Synth 8-3332] Sequential element (T1[3].RC/trc/RS1) is unused and will be removed from module pwr_controller. WARNING: [Synth 8-3332] Sequential element (DAC/cntr2[5].nolabel_line91) is unused and will be removed from module pwr_controller. WARNING: [Synth 8-3332] Sequential element (T3[0].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[1].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[2].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[3].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[4].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[5].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[6].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[7].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[8].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[9].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[10].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[11].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[12].RC/trc/RS1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D0/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D1/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D2/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D3/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D4/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D5/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D6/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D7/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D8/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D9/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D10/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D11/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D12/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D13/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D14/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (regwv/D15/LATCH1) is unused and will be removed from module coil. WARNING: [Synth 8-3332] Sequential element (T3[0].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[1].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[2].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[3].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[4].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[5].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[6].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[7].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[8].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[9].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[10].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[11].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (T3[12].RC/trc/RS1) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[0].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[1].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[2].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[3].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[4].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[5].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[6].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[7].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[8].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[9].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_plasm[10].D1/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[0].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[1].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[2].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[3].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[4].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[5].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[6].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[7].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[8].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[9].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter_sheed[10].D2/LATCH2) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (stop_reg) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (plasm1_reg) is unused and will be removed from module interrupter. WARNING: [Synth 8-3332] Sequential element (counter1[0].nolabel_line42) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter1[1].nolabel_line42) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter1[2].nolabel_line42) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter1[3].nolabel_line42) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter2[0].nolabel_line72) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter2[1].nolabel_line72) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter2[2].nolabel_line72) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter2[3].nolabel_line72) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (counter2[4].nolabel_line72) is unused and will be removed from module USART. WARNING: [Synth 8-3332] Sequential element (REGFB/D0/LATCH1) is unused and will be removed from module frequency_meter. WARNING: [Synth 8-3332] Sequential element (REGFB/D1/LATCH1) is unused and will be removed from module frequency_meter. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[29]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[28]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[27]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[26]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[25]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[24]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[23]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[22]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[21]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[20]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[19]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[18]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[17]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[16]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[15]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[14]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[13]) is unused and will be removed from module GPIO. WARNING: [Synth 8-3332] Sequential element (gpio_reg_reg[12]) is unused and will be removed from module GPIO. INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2677 ; free virtual = 28255 --------------------------------------------------------------------------------- Sort Area is A4/s_axis_cartesian_tdata0_4 : 0 0 : 2168 2168 : Used 1 time 0 Sort Area is A1/s_axis_cartesian_tdata0_0 : 0 0 : 1221 1221 : Used 1 time 0 Sort Area is A1/s_axis_cartesian_tdata0_8 : 0 0 : 1221 1221 : Used 1 time 0 Sort Area is A2/s_axis_cartesian_tdata0_2 : 0 0 : 1221 1221 : Used 1 time 0 Sort Area is A3/s_axis_cartesian_tdata0_3 : 0 0 : 1221 1221 : Used 1 time 0 Sort Area is A2/s_axis_cartesian_tdata0_9 : 0 0 : 891 891 : Used 1 time 0 Sort Area is OUTA1_6 : 0 0 : 666 666 : Used 1 time 0 --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set) +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ |action1024 | (C:0x1)-A*B | 12 | 12 | 1 | - | 25 | 0 | 0 | 0 | - | - | 0 | 0 | |action1024 | (C:0x1)-A*B | 12 | 12 | 1 | - | 25 | 0 | 0 | 0 | - | - | 0 | 0 | |action65536 | (C:0x1)-A*B | 12 | 12 | 1 | - | 32 | 0 | 0 | 0 | - | - | 0 | 0 | |action65536 | (C:0x1)-A*B | 16 | 16 | 1 | - | 32 | 0 | 0 | 0 | - | - | 0 | 0 | |coil | A*B | 12 | 8 | - | - | 20 | 0 | 0 | - | - | - | 0 | 0 | |action1024 | (C:0x1)-A*B | 12 | 12 | 1 | - | 25 | 0 | 0 | 0 | - | - | 0 | 0 | |action1024 | (C:0x1)-A*B | 10 | 10 | 1 | - | 25 | 0 | 0 | 0 | - | - | 0 | 0 | +------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+ Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2658 ; free virtual = 28244 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:29 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2658 ; free virtual = 28244 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:30 ; elapsed = 00:00:30 . Memory (MB): peak = 2368.770 ; gain = 633.266 ; free physical = 2683 ; free virtual = 28271 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- WARNING: [Synth 8-3295] tying undriven pin Block1/design_1_i:sys_rst_n_0 to constant 0 CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin convst_in CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[15] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[14] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[13] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[12] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[11] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[10] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[9] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[8] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[7] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[6] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[5] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[4] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[3] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[2] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[1] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin di_in[0] CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line120/XADC2 has unconnected pin dwe_in CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block2/nolabel_line134/cd has unconnected pin aclk CRITICAL WARNING: [Synth 8-4442] BlackBox module \Block3/nolabel_line156/cd has unconnected pin aclk Извините, я начинающий на форуме. Вот вам лог. Там GPIO не биндятся совсем, я назначил их по правилам. И Всё остальное не биндится, но в логе нет ничего о причине. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
aliceLiddell 0 2 мая Опубликовано 2 мая · Жалоба По поводу комментариев: Это небольшая программа для медиаконвертера, играет музыку. По блокам: Блок 1 это процессор с выходами на UART и pcie для вай-фая. Первый используется для debug процессора, второй для внутреннего debug. Блок 2 это контроллер питания, генерирующий сигнал для нелинейника. С ним всё нормально. Блок 3 это генератор ЧМ сигнала для усилителя. С ним тоже было всё нормально. Блок 4 защита от сверхкоротких импульсов, их у меня есть. Выдаёт сигнал protect на блок 3. Не биндится совсем. Это из-за того, что в блоках с USART предназначенных для передачи по оптике нет синтеза. Блок 5 выдаёт сигналы на блоки 2 и 3. Блок 6 и 7 USARTы. Порты не биндятся совсем. Блок 8. Частотометр. Прошёл проверку. Блок 9 контроль громкости. Volume передаётся в блок 3. Принимает audio_da_volume с uart внутреннего процессора. Нашел ошибку, перепутал вход и выход местами. Блок 10 UART для внутренней отладки схемы. Блок 11 основные входы-выходы. Всё внутри просто перемиксовка битов. Спасибо за внимание. Синтез снова дал сбой. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
Obam 33 2 мая Опубликовано 2 мая · Жалоба ...Схема простейшая для станка на плазме... ...Это небольшая программа для медиаконвертера, играет музыку... Так кто ж на ком стоял? Извините, я начинающий на форуме. 6 годиков... 1 Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
EdgeAligned 55 3 мая Опубликовано 3 мая · Жалоба Даааа, жээээсть 🙂 Чето тут походу ИИ слова составлял - слова есть, смысла нету. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
aliceLiddell 0 3 мая Опубликовано 3 мая · Жалоба Из станка на плазме мы пытались сделать медиаконвертер😄 А ии ничего не может написать сам. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
aliceLiddell 0 3 мая Опубликовано 3 мая · Жалоба Уважаемый модератор. Можно ли переместить тему в соответствующий раздел? Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
makc 197 3 мая Опубликовано 3 мая · Жалоба 1 час назад, aliceLiddell сказал: Уважаемый модератор. Можно ли переместить тему в соответствующий раздел? Раздел вполне соответствует уровню и характеру вопроса. Устное предупреждение: исходники и логи (длинный текст) прикрепляйте к сообщениям в виде файлов (аттачей), а не вставляйте в текст без тега код и спойлеров. В противном случае вы получите предупреждение и посты будут удалены. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
Baza 25 3 мая Опубликовано 3 мая · Жалоба Вспомнил что-то анекдот, про ошибку в коде Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
aliceLiddell 0 3 мая Опубликовано 3 мая · Жалоба Это важно? Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
Maksim_2444 3 3 мая Опубликовано 3 мая · Жалоба В 02.05.2024 в 18:04, aliceLiddell сказал: но в логе нет ничего о причине начните с того, чтоб пофиксить: CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin GMII_ETHERNET_1_tx_en with 1st driver pin 'IBUF_ETH_TEN/O' [/home/typo3/project_4/project_4.srcs/sources_1/new/main.v:209] CRITICAL WARNING: [Synth 8-6859] multi-driven net on pin GMII_ETHERNET_1_tx_en with 2nd driver pin 'Block1/design_1_i/processing_system7_0/ENET1_GMII_TX_EN[0]' [/home/typo3/project_4/project_4.gen/sources_1/bd/design_1/synth/design_1.v:441] первая ссыль в гугл на аналогичную проблему: https://support.xilinx.com/s/question/0D52E00006hplltSAA/synth-86859-multi-driven-net-on-pin-output-error?language=en_US Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
