Приветствую. Большое спасибо за внимание. Продолжаю бороться с ентим датамувером.
Пересобрал свой проект.
В XPS проект имеет вид
добавил стрим ядро, которое данные берет из фифо и по команде выдает датамуверу для трансфера
вот мой .mhs
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 14.3 Build EDK_P.40xd
# Mon Dec 22 18:24:46 2014
# Target Board: xilinx.com ml605 Rev D
# Family: virtex6
# Device: xc6vlx240t
# Package: ff1156
# Speed Grade: -1
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT ddr_memory_we_n = ddr_memory_we_n, DIR = O
PORT ddr_memory_ras_n = ddr_memory_ras_n, DIR = O
PORT ddr_memory_odt = ddr_memory_odt, DIR = O
PORT ddr_memory_dqs_n = ddr_memory_dqs_n, DIR = IO, VEC = [0:0]
PORT ddr_memory_dqs = ddr_memory_dqs, DIR = IO, VEC = [0:0]
PORT ddr_memory_dq = ddr_memory_dq, DIR = IO, VEC = [7:0]
PORT ddr_memory_dm = ddr_memory_dm, DIR = O, VEC = [0:0]
PORT ddr_memory_ddr3_rst = ddr_memory_ddr3_rst, DIR = O
PORT ddr_memory_cs_n = ddr_memory_cs_n, DIR = O
PORT ddr_memory_clk_n = ddr_memory_clk_n, DIR = O, SIGIS = CLK
PORT ddr_memory_clk = ddr_memory_clk, DIR = O, SIGIS = CLK
PORT ddr_memory_cke = ddr_memory_cke, DIR = O
PORT ddr_memory_cas_n = ddr_memory_cas_n, DIR = O
PORT ddr_memory_ba = ddr_memory_ba, DIR = O, VEC = [2:0]
PORT ddr_memory_addr = ddr_memory_addr, DIR = O, VEC = [12:0]
PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT CLK_P = CLK, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
PORT CLK_N = CLK, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
PORT clk10MHz = clock_generator_0_CLKOUT4, DIR = O, SIGIS = CLK, CLK_FREQ = 10000000
PORT ARESETN = master_strm_0_M_AXIS_ARESETN, DIR = I
PORT TREADY = master_strm_0_S_AXIS_TREADY, DIR = O
PORT TDATA = master_strm_0_S_AXIS_TDATA, DIR = I, VEC = [31:0]
PORT TLAST = master_strm_0_S_AXIS_TLAST, DIR = I
PORT TVALID = master_strm_0_S_AXIS_TVALID, DIR = I
PORT cmdsts_awclk = axi_datamover_0_m_axis_s2mm_cmdsts_awclk, DIR = I, SIGIS = CLK
PORT cmdsts_aresetn = axi_datamover_0_m_axis_s2mm_cmdsts_aresetn, DIR = I, SIGIS = RST
PORT cmd_tvalid = axi_datamover_0_s_axis_s2mm_cmd_tvalid, DIR = I
PORT cmd_tready = axi_datamover_0_s_axis_s2mm_cmd_tready, DIR = O
PORT cmd_tdata = axi_datamover_0_s_axis_s2mm_cmd_tdata, DIR = I, VEC = [71:0]
PORT sts_tvalid = axi_datamover_0_m_axis_s2mm_sts_tvalid, DIR = O
PORT sts_tready = axi_datamover_0_m_axis_s2mm_sts_tready, DIR = I
PORT sts_tdata = axi_datamover_0_m_axis_s2mm_sts_tdata, DIR = O, VEC = [7:0]
PORT sts_tkeep = axi_datamover_0_m_axis_s2mm_sts_tkeep, DIR = O
PORT sts_tlast = axi_datamover_0_m_axis_s2mm_sts_tlast, DIR = O
PORT mm2s_aresetn = axi4_0_S_m_axi_mm2s_aresetn, DIR = I, SIGIS = RST
PORT s2mm_aresetn = axi4_0_S_m_axi_s2mm_aresetn, DIR = I, SIGIS = RST
PORT clk100MHz = clk_100_0000MHzMMCM0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT Dcm_locked = proc_sys_reset_0_Dcm_locked
PORT Slowest_sync_clk = clk_100_0000MHzMMCM0
PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
PORT Ext_Reset_In = RESET
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_CLKIN_FREQ = 200000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_GROUP = MMCM0
PARAMETER C_CLKOUT1_FREQ = 200000000
PARAMETER C_CLKOUT1_GROUP = MMCM0
PARAMETER C_CLKOUT2_FREQ = 400000000
PARAMETER C_CLKOUT2_GROUP = MMCM0
PARAMETER C_CLKOUT3_FREQ = 400000000
PARAMETER C_CLKOUT3_GROUP = MMCM0
PARAMETER C_CLKOUT3_BUF = FALSE
PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE
PARAMETER C_CLKOUT4_FREQ = 10000000
PORT LOCKED = proc_sys_reset_0_Dcm_locked
PORT CLKOUT0 = clk_100_0000MHzMMCM0
PORT RST = RESET
PORT CLKOUT3 = clk_400_0000MHzMMCM0_nobuf_varphase
PORT CLKOUT2 = clk_400_0000MHzMMCM0
PORT CLKOUT1 = clk_200_0000MHzMMCM0
PORT CLKIN = CLK
PORT PSCLK = clk_200_0000MHzMMCM0
PORT PSEN = psen
PORT PSINCDEC = psincdec
PORT PSDONE = psdone
PORT CLKOUT4 = clock_generator_0_CLKOUT4
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi4_0
PARAMETER HW_VER = 1.06.a
PORT interconnect_aclk = clk_100_0000MHzMMCM0
PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END
BEGIN axi_v6_ddrx
PARAMETER INSTANCE = DDR3_SDRAM
PARAMETER HW_VER = 1.06.a
PARAMETER C_MEM_PARTNO = MT41J64M16XX-15E
PARAMETER C_DM_WIDTH = 1
PARAMETER C_DQS_WIDTH = 1
PARAMETER C_DQ_WIDTH = 8
PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y8
PARAMETER C_NDQS_COL0 = 1
PARAMETER C_NDQS_COL1 = 0
PARAMETER C_S_AXI_BASEADDR = 0xa4000000
PARAMETER C_S_AXI_HIGHADDR = 0xa7ffffff
PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi_datamover_0.M_AXI_S2MM
BUS_INTERFACE S_AXI = axi4_0
PORT ddr_we_n = ddr_memory_we_n
PORT ddr_ras_n = ddr_memory_ras_n
PORT ddr_odt = ddr_memory_odt
PORT ddr_dqs_n = ddr_memory_dqs_n
PORT ddr_dqs_p = ddr_memory_dqs
PORT ddr_dq = ddr_memory_dq
PORT ddr_dm = ddr_memory_dm
PORT ddr_reset_n = ddr_memory_ddr3_rst
PORT ddr_cs_n = ddr_memory_cs_n
PORT ddr_ck_n = ddr_memory_clk_n
PORT ddr_ck_p = ddr_memory_clk
PORT ddr_cke = ddr_memory_cke
PORT ddr_cas_n = ddr_memory_cas_n
PORT ddr_ba = ddr_memory_ba
PORT ddr_addr = ddr_memory_addr
PORT clk_rd_base = clk_400_0000MHzMMCM0_nobuf_varphase
PORT clk_mem = clk_400_0000MHzMMCM0
PORT clk = clk_200_0000MHzMMCM0
PORT clk_ref = clk_200_0000MHzMMCM0
PORT PD_PSEN = psen
PORT PD_PSINCDEC = psincdec
PORT PD_PSDONE = psdone
END
BEGIN axi_datamover
PARAMETER INSTANCE = axi_datamover_0
PARAMETER HW_VER = 3.00.a
PARAMETER C_INCLUDE_MM2S = 0
PARAMETER C_INCLUDE_S2MM = 1
PARAMETER C_INCLUDE_S2MM_DRE = 0
PARAMETER C_S2MM_BTT_USED = 23
PARAMETER C_S2MM_INCLUDE_SF = 0
PARAMETER C_S2MM_BURST_SIZE = 256
PARAMETER C_S2MM_STSCMD_IS_ASYNC = 1
PARAMETER C_S2MM_STSCMD_FIFO_DEPTH = 4
BUS_INTERFACE M_AXI_S2MM = axi4_0
BUS_INTERFACE S_AXIS_S2MM = master_strm_0_M_AXIS
PORT m_axi_s2mm_aclk = clk_100_0000MHzMMCM0
PORT m_axis_s2mm_cmdsts_awclk = axi_datamover_0_m_axis_s2mm_cmdsts_awclk
PORT m_axis_s2mm_cmdsts_aresetn = axi_datamover_0_m_axis_s2mm_cmdsts_aresetn
PORT s_axis_s2mm_cmd_tvalid = axi_datamover_0_s_axis_s2mm_cmd_tvalid
PORT s_axis_s2mm_cmd_tready = axi_datamover_0_s_axis_s2mm_cmd_tready
PORT s_axis_s2mm_cmd_tdata = axi_datamover_0_s_axis_s2mm_cmd_tdata
PORT m_axis_s2mm_sts_tvalid = axi_datamover_0_m_axis_s2mm_sts_tvalid
PORT m_axis_s2mm_sts_tready = axi_datamover_0_m_axis_s2mm_sts_tready
PORT m_axis_s2mm_sts_tdata = axi_datamover_0_m_axis_s2mm_sts_tdata
PORT m_axis_s2mm_sts_tkeep = axi_datamover_0_m_axis_s2mm_sts_tkeep
PORT m_axis_s2mm_sts_tlast = axi_datamover_0_m_axis_s2mm_sts_tlast
END
BEGIN master_strm
PARAMETER INSTANCE = master_strm_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE M_AXIS = master_strm_0_M_AXIS
PORT ACLK = clk_100_0000MHzMMCM0
PORT S_AXIS_TREADY = master_strm_0_S_AXIS_TREADY
PORT S_AXIS_TDATA = master_strm_0_S_AXIS_TDATA
PORT S_AXIS_TLAST = master_strm_0_S_AXIS_TLAST
PORT S_AXIS_TVALID = master_strm_0_S_AXIS_TVALID
END
результаты функционального моделирования в modelsim
на рисунке виден реади на 4 такта
далее после наполнения фифо считываю данные датамувером
почему сигнал реади (s_axi_s2mm_tready) при появлении сигнала данных (s_axi_s2mm_tvalid) принимает нулевое значение????
То есть при наличии данных и изменении содержимого cmd регистра датамувер пишет после нескольких тактов s_axi_s2mm_tvalid что не готов их принять???
вот картина если я отключаю проверку s_axi_s2mm_tready
стрим пакеты идут, но естественно не далее датамувера, т.к. s_axi_s2mm_tready не проверяется....
