library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VComponents.all;
entity top is
port(clk : in std_logic;
rst : in std_logic;
-- data_in : in std_logic_vector(7 downto 0);
sync_p : out STD_LOGIC;
sync_n : out STD_LOGIC;
adcdata_p : in STD_LOGIC_VECTOR (13 downto 0);
adcdata_n : in STD_LOGIC_VECTOR (13 downto 0);
dacA_p : out std_logic_vector(13 downto 0);
dacA_n : out std_logic_vector(13 downto 0));
end top;
ARCHITECTURE beh OF top IS
component convert2diffpairs
Port (
diff_p : out STD_LOGIC_VECTOR (13 downto 0);
diff_n : out STD_LOGIC_VECTOR (13 downto 0);
data_in : in STD_LOGIC_VECTOR (13 downto 0));
end component;
begin
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i5 : IBUFDS generic map ( DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "DEFAULT") port map (data_in(0), adcdata_p(0), adcdata_n(0));
i6 : IBUFDS generic map ( DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "DEFAULT") port map (data_in(1), adcdata_p(1), adcdata_n(1));
i7 : IBUFDS generic map ( DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "DEFAULT") port map (data_in(2), adcdata_p(2), adcdata_n(2));
i8 : IBUFDS generic map ( DIFF_TERM => FALSE, IBUF_LOW_PWR => TRUE, IOSTANDARD => "DEFAULT") port map (data_in(3), adcdata_p(3), adcdata_n(3));
i41: convert2diffpairs port map(dacA_p, dacA_n, pr(22 downto 9));
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end;
