В том же AXI4-Stream нет ничего емкого в плане ресурсов.
Вот пример подключения "классического" FIFO на AXI4-Stream:
module axi4s_fifo
#(
parameter SIZE = 512,
parameter WIDTH = 8,
parameter TID_WIDTH = 0,
parameter NUM_SYNC = 3,
parameter RST_TYPE = "ASYNC", // "ASYNC",
// "SYNC_SLAVE",
// "SYNC_MASTER"
parameter SIM_INIT = "FALSE" // "TRUE",
// "FALSE"
)
(
// Reset
input axis_aresetn,
// AXI4-Stream (video input)
input s_axis_aclk,
input s_axis_tvalid,
output s_axis_tready,
input [WIDTH-1:0] s_axis_tdata,
input [TID_WIDTH-1:0] s_axis_tid,
input s_axis_tuser, // start of frame
input s_axis_tlast, // end of line
// AXI4-Stream (video output)
input m_axis_aclk,
output m_axis_tvalid,
input m_axis_tready,
output [WIDTH-1:0] m_axis_tdata,
output [TID_WIDTH-1:0] m_axis_tid,
output m_axis_tuser, // start of frame
output m_axis_tlast // end of line
) ;
reg reset_n ;
wire [(WIDTH+TID_WIDTH+1+1)-1:0] s_axis_d ;
wire wrfull ;
wire [(WIDTH+TID_WIDTH+1+1)-1:0] m_axis_q ;
wire rdempty ;
initial begin
if (SIM_INIT == "TRUE") begin
#0.01 ;
if (RST_TYPE != "ASYNC")
reset_n <= 1'b0 ;
end
end
generate
if (RST_TYPE == "ASYNC") begin
always @* begin
reset_n = axis_aresetn ;
end
end
else if (RST_TYPE == "SYNC_SLAVE") begin
always @(posedge s_axis_aclk) begin
reset_n <= axis_aresetn ;
end
end
else if (RST_TYPE == "SYNC_MASTER") begin
always @(posedge m_axis_aclk) begin
reset_n <= axis_aresetn ;
end
end
endgenerate
generate
if (TID_WIDTH > 0) begin
assign s_axis_d = {s_axis_tuser, s_axis_tlast, s_axis_tid, s_axis_tdata} ;
end
else begin
assign s_axis_d = {s_axis_tuser, s_axis_tlast, s_axis_tdata} ;
end
endgenerate
d_c_fifo #(
.DATA_WIDTH (WIDTH+TID_WIDTH+1+1),
.Q_WIDTH (WIDTH+TID_WIDTH+1+1),
.DATA_SIZE (SIZE),
.NUM_SYNC (NUM_SYNC),
.SIM_INIT (SIM_INIT)
)
d_c_fifo_0 (
.reset (~reset_n),
.data (s_axis_d),
.wrreq (s_axis_tvalid & s_axis_tready),
.wrclk (s_axis_aclk),
.rdreq (m_axis_tvalid & m_axis_tready),
.rdclk (m_axis_aclk),
.q (m_axis_q),
.wrempty (),
.wrfull (wrfull),
.rdempty (rdempty),
.rdfull ()
) ;
generate
if (TID_WIDTH > 0) begin
assign {m_axis_tuser, m_axis_tlast, m_axis_tid, m_axis_tdata} = m_axis_q ;
end
else begin
assign {m_axis_tuser, m_axis_tlast, m_axis_tdata} = m_axis_q ;
end
endgenerate
assign s_axis_tready = ~wrfull ;
assign m_axis_tvalid = ~rdempty ;
endmodule
Как видите, это всего лишь переименование сигналов с небольшим количеством логики.
