С TCL скриптом понятно.
Я не понимаю, откуда брать *.mmi файл.
В скомпилированном проекте его нет.
Память я задаю через Verilog, а не через IP.
`timescale 1 ns / 1 ps
module avr_cpu_prog_ram
#(
parameter DATA_SIZE = 4096,
parameter DATA_WIDTH = 16,
parameter INIT_FILE = "",
parameter SIM_INIT = "FALSE"
)
(
input clock_a,
input clock_b,
input addressstall_a,
input addressstall_b,
input [$clog2(DATA_SIZE)-1:0] address_a,
input [$clog2(DATA_SIZE)-1:0] address_b,
input [DATA_WIDTH-1:0] data_a,
input [DATA_WIDTH-1:0] data_b,
input wren_a,
input wren_b,
input enable_out_a,
input enable_out_b,
input aclr_out_a,
input aclr_out_b,
output reg [DATA_WIDTH-1:0] q_a,
output reg [DATA_WIDTH-1:0] q_b
) ;
reg [$clog2(DATA_SIZE)-1:0] address_reg_a ;
wire [$clog2(DATA_SIZE)-1:0] address_mux_a ;
reg [$clog2(DATA_SIZE)-1:0] address_reg_b ;
wire [$clog2(DATA_SIZE)-1:0] address_mux_b ;
reg [DATA_WIDTH-1:0] mem [DATA_SIZE-1:0] /* synthesis syn_ramstyle = "no_rw_check" */ ;
initial begin
#0.01 ;
if (INIT_FILE != "") begin
$readmemh (INIT_FILE, mem) ;
end
if (SIM_INIT == "TRUE") begin
address_reg_a <= 0 ;
address_reg_b <= 0 ;
q_a <= 0 ;
q_b <= 0 ;
end
end
assign address_mux_a = (addressstall_a)? address_reg_a : address_a ;
always @(posedge clock_a) begin
address_reg_a <= address_mux_a ;
if (wren_a)
mem[address_mux_a] <= data_a ;
end
always @(posedge clock_a or posedge aclr_out_a) begin
if (aclr_out_a)
q_a <= 0 ;
else if (enable_out_a)
q_a <= mem[address_reg_a] ;
end
assign address_mux_b = (addressstall_b)? address_reg_b : address_b ;
always @(posedge clock_b) begin
address_reg_b <= address_mux_b ;
if (wren_b)
mem[address_mux_b] <= data_b ;
end
always @(posedge clock_b or posedge aclr_out_b) begin
if (aclr_out_b)
q_b <= 0 ;
else if (enable_out_b)
q_b <= mem[address_reg_b] ;
end
endmodule
