generic, vhdl

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Maverick_ 15

28 августа, 2021

Опубликовано 28 августа, 2021 · Жалоба

Добрый день

есть generic

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.arithmetic_pkg.all;


entity aligner is
	generic(
		UNIT_WIDTH				: integer := 1;
		NUM_UNIT_INPUT			: integer := 16;*
		NUM_UNIT_OUTPUT			: integer := 16; -- must be larger than NUM_UNIT_INPUT
		
		NUM_UNIT_INPUT_WIDTH	: integer := work.arithmetic_pkg.clog2(NUM_UNIT_INPUT+1);*
		NUM_UNIT_OUTPUT_WIDTH	: integer := work.arithmetic_pkg.clog2(NUM_UNIT_OUTPUT+1);
		
		ALIGNED_LEFT			: std_logic := '1'   --set to 1 of aligned to the left, otherwise right
	);
	port(
		clk 				: in std_logic;
		reset_n				: in std_logic;
		
		start				: in std_logic;
		
		input_data			: in std_logic_vector(UNIT_WIDTH*NUM_UNIT_INPUT-1 downto 0);
		input_data_valid	: in std_logic;
		input_num			: in unsigned(NUM_UNIT_INPUT_WIDTH-1 downto 0);
		input_last			: in std_logic;
		task_last_in        : in std_logic; --the last slice of the task
				
		output_data 		: out std_logic_vector(UNIT_WIDTH*NUM_UNIT_OUTPUT-1 downto 0);
		output_data_valid	: out std_logic;
		output_num			: out unsigned(NUM_UNIT_OUTPUT_WIDTH-1 downto 0);
		output_last 		: out std_logic;
		task_last_out       : out std_logic
	);
end entity;

При этом квартус 18.1 ругается

Error (10552): VHDL expression error at aligner.vhd(14): illegal NUM_UNIT_INPUT in expression
Error (10556): VHDL error at aligner.vhd(11): generic "NUM_UNIT_INPUT" cannot be used in its own interface list

Номера строк в которых ошибка отметил звездочкой.

Подскажите пожалуйста как по другому написать чтобы не было ошибки.

Ниже привожу описание arithmetic_pkg

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;

package arithmetic_pkg is

	function clog2(arg: natural) return natural;
	
	function dividor_round_to_ceil(divisor	: integer; dividend : integer) return integer;

end package arithmetic_pkg;

package body arithmetic_pkg is
	function clog2(arg: natural) return natural is
    begin
        if    arg <= 1 then return 0;
        elsif arg <= 2 then return 1;
        elsif arg <= 4 then return 2;
        elsif arg <= 8 then return 3;
        elsif arg <= 16 then return 4;
        elsif arg <= 32 then return 5;
        elsif arg <= 64 then return 6;
        elsif arg <= 128 then return 7;
        elsif arg <= 256 then return 8;
        elsif arg <= 512 then return 9;
        elsif arg <= 1024 then return 10;
        elsif arg <= 2048 then return 11;
        elsif arg <= 4096 then return 12;
        elsif arg <= 8192 then return 13;
        elsif arg <= 16384 then return 14;
        elsif arg <= 32768 then return 15;
        elsif arg <= 65536 then return 16;
        elsif arg <= 131072 then return 17;
        elsif arg <= 262144 then return 18;
        elsif arg <= 524288 then return 19;
        elsif arg <= 1048576 then return 20;
        elsif arg <= 2097152 then return 21;
        elsif arg <= 4194304 then return 22;
        elsif arg <= 8388608 then return 23;
        elsif arg <= 16777216 then return 24;
        elsif arg <= 33554432 then return 25;
        elsif arg <= 67108864 then return 26;
        elsif arg <= 134217728 then return 27;
        elsif arg <= 268435456 then return 28;
        elsif arg <= 536870912 then return 29;
        elsif arg <= 1073741824 then return 30;
        else
            return 31;
        end if;
    end;
	
	function dividor_round_to_ceil(divisor	: integer;
		dividend : integer) return integer is
	begin
		if((dividend mod divisor) = 0)then
			return (dividend/divisor);
		else
			return (dividend/divisor + 1);
		end if;
	end;
	

end package body arithmetic_pkg;