Появился в составе пакета продукт Qsys (beta), однако пока не работают ссылки на документацию онлайн из него на сайте Альтеры
Qsys is a powerful system integration tool that is included as part of the Quartus II software. Qsys captures system-level hardware designs at a high level of abstraction and also automates the task of defining and integrating custom HDL design blocks, commonly referred to as design modules, IP cores, or components. Qsys facilitates design reuse by packaging and making available your custom components and systems. You can use Qsys to integrate your own components with the components that Altera and third-party developers provide. In some cases, you can implement an entire design using components from the Altera component library. During system generation, Qsys automatically creates high-performance interconnect logic from the connectivity you specify, eliminating the error-prone and time-consuming task of writing HDL to specify the system-level connections.
After starting Qsys, you can select and customize the individual components and the ports between them. Qsys combines these components and generates a system module that instantiates these components, and automatically generates the necessary system interconnect to connect the components.
You can use Qsys to construct embedded microprocessor systems that include processors, memory interfaces, and peripherals; however, you can also generate dataflow systems that do not include a processor. Qsys allows you to control bus topologies with multiple masters and slaves.
Qsys provides the following advantages for hardware system design:
- Automates the process of customizing and integrating components
- Supports modular system design
- Supports visualization of large systems
- Supports optimization of interconnect fabric and pipelining within the system
- Integrates fully with the Quartus II software
