[Iouri 0]

http://www.edn.com/contents/images/6372832.pdf

[CaPpuCcino 0]

:1111493779: господа, вешая посты подобного типа, оставляйте хоть какие-нибудь свои комментарии какой целевой аудитории адресовано послание и какую информацию из него пожно получить

[sazh 3]

Самое интересное в этой истории, что тестбенч есть. а вот описания самой схемы нет. Или мой word, или я читать не умеют.

[Doka 4]

to sazh

 

Listing 1: The Dual-Modulus Divider in VHDL

library ieee;
use ieee.std_logic_1164.all;

entity example_dual_mod is
    port(
        reset  : in  std_logic; -- Active-High Synchronous Reset
        clock  : in  std_logic; -- Input Clock
        output : out std_logic  -- Output Baud Clock
    );
end example_dual_mod;

architecture implementation of example_dual_mod is

    -- These parameters calculated according to the text.
    -- This set generates 115200 Hz rate output from 10 MHz
    constant C : integer := 72; -- Sequence Length
    constant B : integer := 43; -- # of times to divide by P
    constant N : integer := 44; -- N should always be P+1
    constant P : integer := 43; -- P should always be N-1

    signal seq_ctr       : integer range 0 to C-1; -- Sequence Counter
    signal dual_mod_load : integer range 0 to N-1; -- Selected load value
    signal dual_mod_ctr  : integer range 0 to N-1; -- Dual Modulus Counter
    signal mux_select    : std_logic; -- Selects between N and P
    signal term_count    : std_logic; -- Dual Modulus Terminal Count
    signal divider       : std_logic; -- Output Divider

begin

    -- This is the sequence counter. Count from C-1 downto 0. Enabled only
    -- when term_count is active. If count is 0, then reload to C-1
    pSeqCount: process(clock)
    begin
        if (rising_edge(clock)) then
            if (reset = '1') then
                seq_ctr <= 0;
            else
                if (term_count = '1') then
                    if (seq_ctr = 0) then
                        seq_ctr <= C-1;
                    else
                        seq_ctr <= seq_ctr - 1;
                    end if;
                end if;
            end if;
        end if;
    end process;

    -- This is the comparison of the current sequence count to the value B
    mux_select <= '1' when (seq_ctr < B) else '0';

    -- This statement implements the modulus selection multiplexer
    dual_mod_load <= (P-1) when (mux_select = '1') else (N-1);

    -- This is the dual-modulus counter. Count from dual_mod_load downto 0.
    -- Counter auto reloads when terminal count is reached.
    pDualModCount: process(clock)
    begin
        if (rising_edge(clock)) then
            if (reset = '1') then
                dual_mod_ctr <= 0;
            else
                if (term_count = '1') then
                    dual_mod_ctr <= dual_mod_load;
                else
                    dual_mod_ctr <= dual_mod_ctr - 1;
                end if;
            end if;
        end if;
    end process;

    -- Detect the terminal count condition
    term_count <= '1' when (dual_mod_ctr = 0) else '0';

    -- The output divide-by-two counter
    pDivider: process(clock)
    begin
        if (rising_edge(clock)) then
            if (reset = '1') then
                divider <= '0';
            elsif (term_count = '1') then
                divider <= not(divider);
            end if;
        end if;
    end process;

    -- Module Output
    output <= divider;

end implementation;

 

 

Listing 2: The Test Bench

library ieee;
use ieee.std_logic_1164.all;

entity dual_mod_tb is
end dual_mod_tb;

architecture testbench of dual_mod_tb is

    signal clock  : std_logic;
    signal reset  : std_logic;
    signal output : std_logic;

begin

    UUT: entity work.example_dual_mod
    port map(
        reset  => reset, -- Active-High Synchronous Reset
        clock  => clock, -- Input Clock
        output => output -- Output Baud Clock
    );

    pClock: process
    begin
        clock <= '0';
        wait for 10 ns;
        clock <= '1';
        wait for 10 ns;
    end process;

    pReset: process
    begin
        reset <= '1';
        wait until rising_edge(clock);
        wait until rising_edge(clock);
        wait until rising_edge(clock);
        reset <= '0';
        wait; -- Forever
    end process;

end testbench;

[sazh 3]

to Doka.

Спасибо. Еще не понял для чего это надо. Но этот парень некоррктно из ресета выходит. Теряет один период системного клока.