Vhdl файл делает Matlab,вот что в нем написано :
-- HDL Code Generation Options:
--
-- TargetLanguage: VHDL
-- TargetDirectory: C:\Users\Skryp\Desktop\MatVHDL
-- TestBenchStimulus: impulse step ramp chirp noise
--
-- Filter Settings:
--
-- Discrete-Time FIR Filter (real)
-- -------------------------------
-- Filter Structure : Direct-Form FIR
-- Filter Length : 5
-- Stable : Yes
-- Linear Phase : Yes (Type 1)
-- Arithmetic : fixed
-- Numerator : s16,19 -> [-6.250000e-002 6.250000e-002)
-- Input : s8,15 -> [-3.906250e-003 3.906250e-003)
-- Filter Internals : Specify Precision
-- Output : s8,34 -> [-7.450581e-009 7.450581e-009)
-- Product : s31,34 -> [-6.250000e-002 6.250000e-002)
-- Accumulator : s32,34 -> [-1.250000e-001 1.250000e-001)
-- Round Mode : convergent
-- Overflow Mode : wrap
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY filter IS
PORT( clk : IN std_logic;
clk_enable : IN std_logic;
reset : IN std_logic;
filter_in : IN std_logic_vector(7 DOWNTO 0); -- sfix8_En15
filter_out : OUT std_logic_vector(7 DOWNTO 0) -- sfix8_En34
);
END filter;
----------------------------------------------------------------
--Module Architecture: filter
----------------------------------------------------------------
ARCHITECTURE rtl OF filter IS
-- Local Functions
-- Type Definitions
TYPE delay_pipeline_type IS ARRAY (NATURAL range <>) OF signed(7 DOWNTO 0); -- sfix8_En15
-- Constants
CONSTANT coeff1 : signed(15 DOWNTO 0) := to_signed(4933, 16); -- sfix16_En19
CONSTANT coeff2 : signed(15 DOWNTO 0) := to_signed(14067, 16); -- sfix16_En19
CONSTANT coeff3 : signed(15 DOWNTO 0) := to_signed(19080, 16); -- sfix16_En19
CONSTANT coeff4 : signed(15 DOWNTO 0) := to_signed(14067, 16); -- sfix16_En19
CONSTANT coeff5 : signed(15 DOWNTO 0) := to_signed(4933, 16); -- sfix16_En19
-- Signals
SIGNAL delay_pipeline : delay_pipeline_type(0 TO 4); -- sfix8_En15
SIGNAL product5 : signed(30 DOWNTO 0); -- sfix31_En34
SIGNAL mul_temp : signed(23 DOWNTO 0); -- sfix24_En34
SIGNAL product4 : signed(30 DOWNTO 0); -- sfix31_En34
SIGNAL mul_temp_1 : signed(23 DOWNTO 0); -- sfix24_En34
SIGNAL product3 : signed(30 DOWNTO 0); -- sfix31_En34
SIGNAL mul_temp_2 : signed(23 DOWNTO 0); -- sfix24_En34
SIGNAL product2 : signed(30 DOWNTO 0); -- sfix31_En34
SIGNAL mul_temp_3 : signed(23 DOWNTO 0); -- sfix24_En34
SIGNAL product1_cast : signed(31 DOWNTO 0); -- sfix32_En34
SIGNAL product1 : signed(30 DOWNTO 0); -- sfix31_En34
SIGNAL mul_temp_4 : signed(23 DOWNTO 0); -- sfix24_En34
SIGNAL sum1 : signed(31 DOWNTO 0); -- sfix32_En34
SIGNAL add_temp : signed(32 DOWNTO 0); -- sfix33_En34
SIGNAL sum2 : signed(31 DOWNTO 0); -- sfix32_En34
SIGNAL add_temp_1 : signed(32 DOWNTO 0); -- sfix33_En34
SIGNAL sum3 : signed(31 DOWNTO 0); -- sfix32_En34
SIGNAL add_temp_2 : signed(32 DOWNTO 0); -- sfix33_En34
SIGNAL sum4 : signed(31 DOWNTO 0); -- sfix32_En34
SIGNAL add_temp_3 : signed(32 DOWNTO 0); -- sfix33_En34
SIGNAL output_typeconvert : signed(7 DOWNTO 0); -- sfix8_En34
SIGNAL output_register : signed(7 DOWNTO 0); -- sfix8_En34
BEGIN
-- Block Statements
Delay_Pipeline_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
delay_pipeline(0 TO 4) <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
delay_pipeline(0) <= signed(filter_in);
delay_pipeline(1 TO 4) <= delay_pipeline(0 TO 3);
END IF;
END IF;
END PROCESS Delay_Pipeline_process;
mul_temp <= delay_pipeline(4) * coeff5;
product5 <= resize(mul_temp, 31);
mul_temp_1 <= delay_pipeline(3) * coeff4;
product4 <= resize(mul_temp_1, 31);
mul_temp_2 <= delay_pipeline(2) * coeff3;
product3 <= resize(mul_temp_2, 31);
mul_temp_3 <= delay_pipeline(1) * coeff2;
product2 <= resize(mul_temp_3, 31);
product1_cast <= resize(product1, 32);
mul_temp_4 <= delay_pipeline(0) * coeff1;
product1 <= resize(mul_temp_4, 31);
add_temp <= resize(product1_cast, 33) + resize(product2, 33);
sum1 <= add_temp(31 DOWNTO 0);
add_temp_1 <= resize(sum1, 33) + resize(product3, 33);
sum2 <= add_temp_1(31 DOWNTO 0);
add_temp_2 <= resize(sum2, 33) + resize(product4, 33);
sum3 <= add_temp_2(31 DOWNTO 0);
add_temp_3 <= resize(sum3, 33) + resize(product5, 33);
sum4 <= add_temp_3(31 DOWNTO 0);
output_typeconvert <= sum4(7 DOWNTO 0);
Output_Register_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
output_register <= (OTHERS => '0');
ELSIF clk'event AND clk = '1' THEN
IF clk_enable = '1' THEN
output_register <= output_typeconvert;
END IF;
END IF;
END PROCESS Output_Register_process;
-- Assignment Statements
filter_out <= std_logic_vector(output_register);
END rtl;
Я также находил на этом форуме пример VHDL кода фильтра (от пользователя Михаил_К);генерировал VHDL с помощью программы с Opencores ,
но в железе не заработал фильтр.Я думаю,что все-таки неправильно собираю схему в Shematic,но разобраться немогу :-(
