Всем привет. Хочу обратиться за советом по проблеме.
Имеем Kintex7 и 2 чипа DDR3. В чистый проект запиливаю 2 контроллера на каждый чип (mig корка позволяет указывать в одном визарде параметры сразу для 2х контроллеров). В итоге при использовании example дизайна в качестве основы компиляция выдаёт следующее:
Критикал варнинги:
Implementation
Design Initialization
[Vivado 12-2285] Cannot set LOC property of instance 'example_top_ddr3_inst/u_mig_7series_0/u_mig_7series_0_mig/c1_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i', Instance example_top_ddr3_inst/u_mig_7series_0/u_mig_7series_0_mig/c1_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i can not be placed in PHY_CONTROL of site PHY_CONTROL_X1Y1 because the bel is occupied by example_top_ddr3_inst/u_mig_7series_0/u_mig_7series_0_mig/c0_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i. This could be caused by bel constraint conflict ["d:/Work/prj/XT_modulator/FPGA/XTM_3/xtm.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc":645]
[Vivado 12-2285] Cannot set LOC property of instance 'example_top_ddr3_inst/u_mig_7series_0/u_mig_7series_0_mig/c1_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i', Instance example_top_ddr3_inst/u_mig_7series_0/u_mig_7series_0_mig/c1_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i can not be placed in PHASER_REF of site PHASER_REF_X1Y1 because the bel is occupied by example_top_ddr3_inst/u_mig_7series_0/u_mig_7series_0_mig/c0_u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i. This could be caused by bel constraint conflict ["d:/Work/prj/XT_modulator/FPGA/XTM_3/xtm.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc":648]
Фолты:
Place Design
[Place 30-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'phaser_in_gen.phaser_in'
[Place 30-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'phaser_out'
[Place 30-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'phaser_in_gen.phaser_in'
[Place 30-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'phaser_out'
[Place 30-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'phaser_ref_i'
[Place 30-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'phy_control_i'
[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
По фолтам видно что есть незаконстрейненые компоненты, хотя в xdc они указаны. XDC судя по 1м варнингам - находит и использует его. Возможно что фолты - следствие ошибки указанной в варнингах.
Варниги выдаёт не спроста, если посмотреть в XDC (сгенерённый визардом, то есть руками я его не трогал) то там явно видно что один и тот же ресурс назначается 2 раза для каждого из контроллеров:
для 1го
set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */c0_u_memc_ui_top_std/*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]
set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */c0_u_memc_ui_top_std/*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
и для 2го
set_property LOC PHY_CONTROL_X1Y0 [get_cells -hier -filter {NAME =~ */c1_u_memc_ui_top_std/*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]
set_property LOC PHY_CONTROL_X1Y1 [get_cells -hier -filter {NAME =~ */c1_u_memc_ui_top_std/*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
То есть PHY_CONTROL_X1Y1 юзается 2 раза на что и указывает 1й варнинг (2й также но на PHASER_REF_X1Y1)
Были ли у кого такие проблемы и как их решать ?
Пробовал генерить отдельно для каждого чипа (для каждой группы пинов) 2 проекта, всё так же как и в смежном - используется один и тот же PHY_CONTROL_X1Y1 и PHASER_REF_X1Y1
