Добрый день, делаю дискретно косинусное преобразование в среде quarus II но есть нюанс. Выдает ошибку Error (10414): VHDL Unsupported Feature error at main.vhd(13): cannot synthesize non-constant real objects or values, на мои созданные типы. В чем может быть проблема?
Первый файл:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package add is
type matrixreal is array(0 to 7, 0 to 7) of real range -255.0 to 255.0;
end package add;
Второй файл
Возможно ошибок еще много, еще изучаю vhdl язык.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
use work.add.all;
entity main is
port (
Clk : in std_logic;
Start : in std_logic;
Din : in matrixreal;
Done : out std_logic;
Dout : out matrixreal
);
end main;
architecture main of main is
begin
process
variable i, j, k: INTEGER;
variable OutBlock : matrixreal;
variable temp : matrixreal;
variable dct : matrixreal;
variable dctt : matrixreal;
variable OutAnother: matrixreal;
begin
dct := (
(0.354, 0.354, 0.354, 0.354, 0.354, 0.354, 0.354, 0.354),
(0.490, 0.416, 0.278, 0.098, -0.098, -0.278, -0.416, -0.490),
(0.462, 0.191, -0.191, -0.462, -0.462, -0.191, 0.191, 0.462),
(0.416, -0.098, -0.490, -0.278, 0.278, 0.490, 0.098, -0.416),
(0.354, -0.354, -0.354, -0.354, 0.354, -0.354, -0.354, 0.354),
(0.278, -0.490, 0.098, 0.416, -0.416, -0.098, 0.490, -0.278),
(0.191, 0.462, 0.462, -0.191, -0.191, 0.462, -0.462, 0.191),
(0.098, 0.278, 0.416, -0.490, 0.490, -0.416, 0.278, -0.098));
wait until Start = '1';
Done <= '0';
for i in 0 to 7 loop
for j in 0 to 7 loop
temp(i,j) := 0.0;
OutBlock(i,j) := 0.0;
Dout(i,j) <= 0.0;
end loop;
end loop;
for i in 0 to 7 loop
for j in 0 to 7 loop
for k in 0 to 7 loop
temp(i,j) := temp(i,j) + dct(i,k) * Din(k,j);
end loop;
end loop;
end loop;
for i in 0 to 7 loop
for j in 0 to 7 loop
dctt(i,j) := temp(j,i);
end loop;
end loop;
for i in 0 to 7 loop
for j in 0 to 7 loop
for k in 0 to 7 loop
OutBlock(i,j) := OutBlock(i,j) + dct(i,k) * dctt(k,j);
end loop;
end loop;
end loop;
for i in 0 to 7 loop
for j in 0 to 7 loop
OutAnother(i,j) := OutBlock(j,i);
end loop;
end loop;
wait until Clk = '1' and Clk'event;
Done <= '1';
for i in 0 to 7 loop
for j in 0 to 7 loop
wait until Clk = '1' and Clk'event;
Done <= '0';
Dout(i,j)<= OutAnother(i,j);
end loop;
end loop;
end process;
end main;
