[Iouri 0]

Господа,

 

 

Подскажите как в Квартусе 5.0 разрешить пул ап резистор через аттрибут

использую MAX2 пишу на ВХДЛ

 

 

Спасибо

[SM 0]

Называется "Weak pullup resistor" в разделе "IO Features". На сколько я знаю разрешать это надо через assignment editor.

[Leka 0]

Раздел "Logic Options", атрибуты можно включать так (пример на Verilog, Qii5.1):

input d /* synthesis altera_attribute = "virtual_pin=on" */;

output q /* synthesis altera_attribute = "weak_pull_up_resistor=on" */;

Изменено 7 декабря, 2005 пользователем Leka

[Iouri 0]

If someone has interest here

 

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.ALL;

--USE ieee.std_logic_signed.ALL;

USE ieee.std_logic_unsigned.ALL;

 

ENTITY test_attrib IS

 

PORT

(

clk : IN STD_LOGIC;

ena : IN STD_LOGIC;

count_out : OUT std_logic_vector(7 downto 0)

);

 

END test_attrib;

 

ARCHITECTURE rtl OF test_attrib IS

 

 

 

attribute chip_pin : string;

attribute chip_pin of clk : signal is "2";

attribute chip_pin of ena : signal is "3";

 

 

 

attribute chip_pin of count_out : signal is "47, 48, 49, 50, 51, 52, 53, 54";

 

attribute altera_attribute : string;

-- Attribute set on architecture, not entity

attribute altera_attribute of clk : signal is "WEAK_PULL_UP_RESISTOR=ON";

attribute altera_attribute of ena : signal is "WEAK_PULL_UP_RESISTOR=ON";

-- attribute altera_attribute of count_out : signal is "IO_STANDARD=LVTTL";

attribute altera_attribute of count_out : signal is "CURRENT_STRENGTH_NEW=8MA";

 

SIGNAL count : std_logic_vector(31 downto 0);

 

BEGIN

 

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk = '1') THEN

IF ena = '1' THEN

count <= count + 1;

END IF;

END IF;

END PROCESS;

 

count_out <= count(31 downto 24);

 

END rtl;