AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба Добрый день. Решил написать простейшее прерывание как бы самостоятельно, без помощи кубической интерполяции. И вот, после вроде успешного правильного запуска RCC и далее по коду, что у меня не происходит возникновение прерывания Таймера TIM2 - см. код ниже. Возможно пропустил включение тактирования модуля NVIC (а оно отдельно есть?) или еще что-то. Подскажите кто в теме. Спасибо большое. int main(void) { SCB->CPACR |= (0xF << 20); // Enable floating-point unit. SystemInit(); SystemClock_Config(); // также в конце получим SystemCoreClock GPIO_BaseInit(); /* ------ Enable MCO1 (PA8) ------ */ RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN; // включим тактирование порта 'PA' GPIOA->MODER &= ~GPIO_MODER_MODE8; // обнулим поле 'MODER8' GPIOA->MODER |= GPIO_MODER_MODE8_1; // Alternative PP GPIOA->OSPEEDR |= GPIO_OSPEEDR_OSPEED8; // Very high speed RCC->CFGR |= RCC_CFGR_MCO1; // Source PLL1Q RCC->CFGR &= ~RCC_CFGR_MCO1PRE_0; // 0-bit to '0' (out div by 4) RCC->CFGR |= RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2; // 1 & 2 bits '1' (out div by 4) /* ------------------------------- */ __IO uint32_t tmpreg; SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); // Enable the TIM2 clock. /* Delay after an RCC peripheral clock enabling */ tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN); (void)(tmpreg); NVIC_SetPriority(TIM2_IRQn, 0x03); // Enable the NVIC interrupt for TIM2. NVIC_EnableIRQ(TIM2_IRQn); __enable_irq(); TIM2->CR1 &= ~(TIM_CR1_CEN); // Start by making sure the timer's 'counter' is off. (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST); // Next, reset the peripheral. // Set the timer prescaler/autoreload timing registers. (These are 16-bit timers, so this won't work with > 65MHz.) TIM2->PSC = SystemCoreClock / 1000; TIM2->ARR = 500; // ms // Send an update event to reset the timer and apply settings. TIM2->EGR |= TIM_EGR_UG; // Enable the hardware interrupt. TIM2->DIER |= TIM_DIER_UIE; // Enable the timer. TIM2->CR1 |= TIM_CR1_CEN; /* Loop forever */ for (;;); } void TIM2_IRQhandler(void) { // Handle a timer 'update' interrupt event if (TIM2->SR & TIM_SR_UIF) { TIM2->SR &= ~(TIM_SR_UIF); // Toggle the LED output pin (пин 'PB1'). GPIOB->ODR ^= (1 << LED_PIN); } } (также приведу код функции запуска RCC - простыня там пока что): Скрытый текст StatusTypeDef SystemClock_Config(void) { /* Supply configuration update enable */ /* Check if supply source was configured */ if (((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) == 0U) { /* Supply configuration update locked, can't apply a new supply config */ if ((PWR->CR3 & (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)) != PWR_CR3_LDOEN) return S_ERROR; } /* Set the power supply configuration */ MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), PWR_CR3_LDOEN); /* Get tick */ uint32_t tickstart = 0; /* Wait till voltage level flag is set */ while (((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) == 0U) { if (++tickstart > S_TIMEOUT_VALUE) return S_ERROR; } /* PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale */ #define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) #define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) /* Configure the main internal regulator output voltage */ #define __REGULATOR__ PWR_REGULATOR_VOLTAGE_SCALE1 __IO uint32_t tmpreg = 0x00; /* Check the voltage scaling to be configured */ if ((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) { /* Configure the Voltage Scaling 1 */ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); /* Delay after setting the voltage scaling */ tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); /* Enable the PWR overdrive */ SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); /* Delay after setting the syscfg boost setting */ tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); } else { /* Disable the PWR overdrive */ CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); /* Delay after setting the syscfg boost setting */ tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); /* Configure the Voltage Scaling x */ MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); /* Delay after setting the voltage scaling */ tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); } while (!((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY)) { } /*--------------------------------------------------------------------------------------------*/ #define RCC_FLAG_MASK ((uint8_t)0x1F) /* The clock source used as system clock. The returned value can be one * of the following: * - RCC_CFGR_SWS_CSI: CSI used as system clock. * - RCC_CFGR_SWS_HSI: HSI used as system clock. * - RCC_CFGR_SWS_HSE: HSE used as system clock. * - RCC_CFGR_SWS_PLL: PLL used as system clock. */ const uint32_t temp_sysclksrc = ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)); const uint32_t temp_pllckselr = RCC->PLLCKSELR; /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if ((temp_sysclksrc == RCC_CFGR_SWS_HSE) || ((temp_sysclksrc == RCC_CFGR_SWS_PLL1) && ((temp_pllckselr & RCC_PLLCKSELR_PLLSRC) == RCC_PLLCKSELR_PLLSRC_HSE))) { if ((((((((RCC_FLAG_HSERDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_HSERDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_HSERDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_HSERDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_HSERDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) != 0U) { return S_ERROR; } } else { /* Set the new HSE configuration - HSE ON */ SET_BIT(RCC->CR, RCC_CR_HSEON); /* Get Start Tick*/ tickstart = 0; /* Wait till HSE is disabled */ if ((((((((RCC_FLAG_HSERDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_HSERDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_HSERDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_HSERDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_HSERDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) != 0U) { if (++tickstart > S_TIMEOUT_VALUE) { return S_TIMEOUT; } } } /* below we accept PLL is used as system clock */ MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, RCC_PLLSOURCE_HSE); tickstart = 0; /* Check RCC flag: PLL1 clock ready or not */ while ((((((((RCC_FLAG_PLLRDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_PLLRDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_PLLRDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_PLLRDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_PLLRDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) != 0) { if (++tickstart > S_TIMEOUT_VALUE) return S_TIMEOUT; } /*--------------------------------------------------------------------------------------------*/ #define __RCC_PLLSOURCE__ RCC_PLLSOURCE_HSE #define __PLLM1__ 5 /** Divide PLL Source Mux: DIVM1 = 5 */ #define __PLLN1__ 144 /** Multipply: DIVN1 = 144 */ #define __PLLP1__ 2 /** Divide: DIVP1 = 2 */ #define __PLLQ1__ 15 /** Divide: DIVQ1 = 15 */ #define __PLLR1__ 2 /** Divide: DIVR1 = 2 */ /* в результате этого на верхнем выходе будут: PLL1Q = 48MHz, PLL1R = 360MHz */ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1), ((__RCC_PLLSOURCE__) | ((__PLLM1__) << 4U))); WRITE_REG(RCC->PLL1DIVR, ((((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); /*--------------------------------------------------------------------------------------------*/ /* Disable PLLFRACN */ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); /* Configure PLL PLL1FRACN to 0 */ MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)0 << RCC_PLL1FRACR_FRACN1_Pos); /* RCC_PLL1_VCI_Range RCC PLL1 VCI Range */ #define RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0 /* Clock range frequency between 1 and 2 MHz */ #define RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1 /* Clock range frequency between 2 and 4 MHz */ #define RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2 /* Clock range frequency between 4 and 8 MHz */ #define RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3 /* Clock range frequency between 8 and 16 MHz */ /* Select PLL1 input reference frequency range: VCI */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, RCC_PLL1VCIRANGE_2); /* RCC_PLL1_VCO_Range RCC PLL1 VCO Range */ #define RCC_PLL1VCOWIDE (0x00000000U) #define RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL /* Select PLL1 output frequency range : VCO */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, RCC_PLL1VCOWIDE); /* Enable PLL System Clock output. */ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN); /* Enable PLL1Q Clock output. */ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN); /* Enable PLL1R Clock output. */ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN); /* Enable Fractional Part Of The Multiplication Factor of PLL1 VCO - PLL1FRACN */ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN); /* Enable the main PLL. After enabling the main PLL, the application software should wait on PLLRDY * flag to be set indicating that PLL clock is stable and can be used as system clock source. */ SET_BIT(RCC->CR, RCC_CR_PLL1ON); /* Get Start Tick*/ tickstart = 0; /* Wait till PLL is ready */ while ((((((((RCC_FLAG_PLLRDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_PLLRDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_PLLRDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_PLLRDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_PLLRDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) != 0) { if (++tickstart > S_TIMEOUT_VALUE) return S_TIMEOUT; } /*--------------------------------------------------------------------------------------------*/ /* Initializes the CPU, AHB and APB buses clocks */ /* RCC System Clock Type */ #define RCC_CLOCKTYPE_SYSCLK (0x00000001U) #define RCC_CLOCKTYPE_HCLK (0x00000002U) #define RCC_CLOCKTYPE_D1PCLK1 (0x00000004U) #define RCC_CLOCKTYPE_PCLK1 (0x00000008U) #define RCC_CLOCKTYPE_PCLK2 (0x00000010U) #define RCC_CLOCKTYPE_D3PCLK1 (0x00000020U) uint32_t ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1; /* The clock source (SYSCLKS) used as system clock */ uint32_t SYSCLKSource = RCC_CFGR_SW_PLL1; /* The system clock divider */ uint32_t SYSCLKDivider = RCC_D1CFGR_D1CPRE_DIV1; /* The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). */ uint32_t AHBCLKDivider = RCC_D1CFGR_HPRE_DIV2; /* The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK). */ uint32_t APB3CLKDivider = RCC_D1CFGR_D1PPRE_DIV2; /* The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). */ uint32_t APB1CLKDivider = RCC_D2CFGR_D2PPRE1_DIV2; /* The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). */ uint32_t APB2CLKDivider = RCC_D2CFGR_D2PPRE2_DIV2; /* The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK). */ uint32_t APB4CLKDivider = RCC_D3CFGR_D3PPRE_DIV2; /* FLASH Two Latency cycles */ uint32_t FLatency = FLASH_ACR_LATENCY_2WS; /* Increasing the BUS frequency divider */ /*-------------------------- D1PCLK1/CDPCLK1 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) { if (APB3CLKDivider > (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) { MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, APB3CLKDivider); } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { if (APB1CLKDivider > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) { MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, APB1CLKDivider); } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { if (APB2CLKDivider > (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) { MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, APB2CLKDivider); } } /*-------------------------- D3PCLK1 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) { if (APB4CLKDivider > (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) { MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, APB4CLKDivider); } } /*-------------------------- HCLK Configuration --------------------------*/ if ((ClockType & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { if (AHBCLKDivider > (RCC->D1CFGR & RCC_D1CFGR_HPRE)) { /* Set the new HCLK clock divider */ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, AHBCLKDivider); } } /*------------------------- SYSCLK Configuration -------------------------*/ if ((ClockType & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) { MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, SYSCLKDivider); /* HSE is selected as System Clock Source */ if (SYSCLKSource == RCC_CFGR_SW_HSE) { /* Check the HSE ready flag */ if ((((((((RCC_FLAG_HSERDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_HSERDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_HSERDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_HSERDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_HSERDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) == 0U) { return S_ERROR; } } /* PLL is selected as System Clock Source */ else if (SYSCLKSource == RCC_CFGR_SW_PLL1) { /* Check the PLL ready flag */ if ((((((((RCC_FLAG_PLLRDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_PLLRDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_PLLRDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_PLLRDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_PLLRDY) & RCC_FLAG_MASK))) == 0U) ? 1U : 0U) == 0U) { return S_ERROR; } } /* CSI is selected as System Clock Source */ else if (SYSCLKSource == RCC_CFGR_SW_CSI) { /* Check the PLL ready flag */ if ((((((((RCC_FLAG_CSIRDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_CSIRDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_CSIRDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_CSIRDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_CSIRDY) & RCC_FLAG_MASK))) == 0U) ? 1U : 0U) == 0U) { return S_ERROR; } } /* HSI is selected as System Clock Source */ else { /* Check the PLL ready flag */ if ((((((((RCC_FLAG_HSIRDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_HSIRDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_HSIRDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_HSIRDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_HSIRDY) & RCC_FLAG_MASK))) == 0U) ? 1U : 0U) == 0U) { return S_ERROR; } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, SYSCLKSource); /* Get Start Tick*/ tickstart = 0; while ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS) != (SYSCLKSource << RCC_CFGR_SWS_Pos)) { if (++tickstart > S_TIMEOUT_VALUE) return S_TIMEOUT; } } /* Decreasing the BUS frequency divider */ /*-------------------------- HCLK Configuration --------------------------*/ if ((ClockType & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) { if (AHBCLKDivider < (RCC->D1CFGR & RCC_D1CFGR_HPRE)) { /* Set the new HCLK clock divider */ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, AHBCLKDivider); } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)FLatency); /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY) != FLatency) { return S_ERROR; } } /*-------------------------- D1PCLK1/CDPCLK Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1) { if (APB3CLKDivider < (RCC->D1CFGR & RCC_D1CFGR_D1PPRE)) { MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, APB3CLKDivider); } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) { if (APB1CLKDivider < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE1)) { MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, APB1CLKDivider); } } /*-------------------------- PCLK2 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) { if (APB2CLKDivider < (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2)) { MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, APB2CLKDivider); } } /*-------------------------- D3PCLK1/SRDPCLK1 Configuration ---------------------------*/ if ((ClockType & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1) { if (APB4CLKDivider < (RCC->D3CFGR & RCC_D3CFGR_D3PPRE)) { MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, APB4CLKDivider); } } uint32_t common_system_clock = HAL_RCC_GetSysClockFreq() >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU); SystemD2Clock = common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU); /* Update the SystemCoreClock global variable */ SystemCoreClock = common_system_clock; /*--------------------------------------------------------------------------------------------*/ #define RCC_PERIPHCLK_RNG (0x00020000U) #define RCC_PERIPHCLK_LTDC (0x20000000U) #define RCC_PERIPHCLK_SPI5 (0x00002000U) #define RCC_PERIPHCLK_I2C2 (0x00000008U) #define RCC_PERIPHCLK_USB (0x00040000U) #define RCC_PERIPHCLK_FMC (0x01000000U) uint32_t PeriphClockSelection = RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_SPI5 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC; /* Division factor for PLL3 VCO input clock. Must be a number between 1 and 63. */ uint32_t PLL3M = 25; /* Multiplication factor for PLL3 VCO output clock. Must be between 4 and 512. */ uint32_t PLL3N = 150; /* Division factor for system clock. Must be between 2 and 128. Odd division factors are not allowed. */ uint32_t PLL3P = 2; /* Division factor for peripheral clocks. Must be between 1 and 128. */ uint32_t PLL3Q = 5; /* Division factor for peripheral clocks. Must be between 1 and 128. */ uint32_t PLL3R = 5; /* PLL3 clock Input range. Must be a value of RCC PLL3 VCI Range. */ uint32_t PLL3RGE = RCC_PLLCFGR_PLL3RGE_0; /* Clock range frequency between 1 and 2 MHz */ /* PLL3 clock Output range. Must be a value of RCC PLL3 VCO Range. */ uint32_t PLL3VCOSEL = RCC_PLLCFGR_PLL3VCOSEL; /* Fractional Part Of The Multiplication Factor for PLL3 VCO. Should be between 0 and 8191 */ uint32_t PLL3FRACN = 0; #define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U) #define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U) #define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U) /*------------------------------------------- LTDC -------------------------------------------*/ /* Disable PLL3. */ CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); /* Get Start Tick. */ tickstart = 0; /* Wait till PLL3 is ready */ while ((((((((RCC_FLAG_PLL3RDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_PLL3RDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_PLL3RDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_PLL3RDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_PLL3RDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) != 0) { if (++tickstart > S_TIMEOUT_VALUE) return S_TIMEOUT; } /* Configure the PLL3 multiplication and division factors. */ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_DIVM3), (PLL3M <<20U)); WRITE_REG(RCC->PLL3DIVR, (((PLL3N - 1U ) & RCC_PLL3DIVR_N3) | (((PLL3P -1U ) << 9U) & RCC_PLL3DIVR_P3) | (((PLL3Q -1U) << 16U) & RCC_PLL3DIVR_Q3) | (((PLL3R - 1U) << 24U) & RCC_PLL3DIVR_R3))); /* Select PLL3 input reference frequency range: VCI */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, PLL3RGE); /* Select PLL3 output frequency range: VCO (RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz) */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, PLL3VCOSEL); /* Disable PLL3FRACN: Fractional Part Of The Multiplication Factor of PLL3 VCO. */ CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); /* Configures PLL3 clock Fractional Part Of The Multiplication Factor. */ MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)PLL3FRACN << RCC_PLL3FRACR_FRACN3_Pos); /* Enable PLL3FRACN: Fractional Part Of The Multiplication Factor of PLL3 VCO. */ SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN); #define DIVIDER_P_UPDATE 0U #define DIVIDER_Q_UPDATE 1U #define DIVIDER_R_UPDATE 2U uint32_t Divider = DIVIDER_R_UPDATE; /* Enable the PLL3 clock output. */ if (Divider == DIVIDER_P_UPDATE) { SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN); } else if (Divider == DIVIDER_Q_UPDATE) { SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN); } else { SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN); } /* Enable PLL3. */ SET_BIT(RCC->CR, RCC_CR_PLL3ON); /* Get Start Tick. */ tickstart = 0; /* Wait till PLL3 is ready. */ while ((((((((RCC_FLAG_PLL3RDY) >> 5U) == 1U) ? RCC->CR : ((((RCC_FLAG_PLL3RDY) >> 5U) == 2U) ? RCC->BDCR : ((((RCC_FLAG_PLL3RDY) >> 5U) == 3U) ? RCC->CSR : ((((RCC_FLAG_PLL3RDY) >> 5U) == 4U) ? RCC->RSR : RCC->CIFR)))) & (1UL << ((RCC_FLAG_PLL3RDY) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) == 0) { if (++tickstart > S_TIMEOUT_VALUE) return S_TIMEOUT; } /*--------------------------------------------------------------------------------------------*/ /* Enable the USB voltage detector */ SET_BIT (PWR->CR3, PWR_CR3_USB33DEN); return S_OK; } void GPIO_BaseInit(void) { // включим тактирование порта 'PB' RCC->AHB4ENR |= RCC_AHB4ENR_GPIOBEN; // обнулим поле 'MODER1' GPIOB->MODER &= ~GPIO_MODER_MODE1; // пин 'PB1' настраиваем как 'push-pull' ('general-purpose', #6.4.1, табл. 21 даташита) GPIOB->MODER |= GPIO_MODER_MODE1_0; // устанавливаем '0' на пине 'PB1' (анод светодиода подключен на +3.3V) GPIOB->BSRR |= GPIO_BSRR_BR1; } Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
haker_fox 60 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 10 minutes ago, AleksBak said: Возможно пропустил включение тактирования модуля NVIC Насколько я знаю, такирование NVIC не включается, т.к. прерывания доступны после старта ядра Cortex. Не вдаваясь в суть вашего кода скажу, что для возникновения прерыания необходимо: 1. Включить данное прерывание в периферии. 2. Включить данное прерывание в NVIC (здесь сознательно ничего не говорю о выставлении приоритета и очистке ожидающего прерывания). 3. Глобально прерывания не должны быть запрещены. 4. Вход в обработчик произойдёт, как только к трём первым условиям будет выставлен флаг прерывания периферии в статусном регистре. Поэтому, вы в отладчике можете вручную в регистре ISR ткнуть фалжок, и посмотреть, перейдёт ли процессор на ваш обработчик. Там в таблице векторов можно поставить точку останова. Так вы хотя бы будете знать, что минимум условий у вас соблюдён. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 22 минуты назад, haker_fox сказал: Поэтому, вы в отладчике можете вручную в регистре ISR ткнуть фалжок, и посмотреть, перейдёт ли процессор на ваш обработчик. Использую отладчик так как Вы и описали. В результате - не переходит и не возникает это прерывание. Все 3 первые из Ваших перечисленных пунктов в коде у меня (см. код выше) вроде выполнены. Спасибо. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
jcxz 184 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 24 минуты назад, haker_fox сказал: ... 4. Вход в обработчик произойдёт, как только к трём первым условиям будет выставлен флаг прерывания периферии в статусном регистре. 5. Задать положение таблицы прерываний. 6. Прописать соответствующий вектор таблицы прерываний на нужный ISR. 7. Отделить мух от котлет определить в чём именно проблема: с вызовом ISR или настройкой таймера? Для чего использовать соответствующие регистры NVIC (для просмотра статуса ожидающего прерывания и для программного возбуждения прерывания). Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 3 минуты назад, jcxz сказал: 5. Задать положение таблицы прерываний. 6. Прописать соответствующий вектор таблицы прерываний на нужный ISR. Это все вроде происходит в коде (извините про него забыл привести инф-цию) - "startup_stm32h743iitx.s" Скрытый текст /** ****************************************************************************** * @file startup_stm32h743iitx.s * @author Auto-generated by STM32CubeIDE * @brief STM32H743IITx device vector table for GCC toolchain. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, * - Set the vector table entries with the exceptions ISR address * - Branches to main in the C library (which eventually * calls main()). ****************************************************************************** * @attention * * <h2><center>© Copyright (c) 2020 STMicroelectronics. * All rights reserved.</center></h2> * * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ .syntax unified .cpu cortex-m7 .fpu softvfp .thumb .global g_pfnVectors .global Default_Handler /* start address for the initialization values of the .data section. defined in linker script */ .word _sidata /* start address for the .data section. defined in linker script */ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata /* start address for the .bss section. defined in linker script */ .word _sbss /* end address for the .bss section. defined in linker script */ .word _ebss /** * @brief This is the code that gets called when the processor first * starts execution following a reset event. Only the absolutely * necessary set is performed, after which the application * supplied main() routine is called. * @param None * @retval : None */ .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack mov sp, r0 /* set stack pointer */ /* Call the clock system intitialization function.*/ bl SystemInit /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata ldr r1, =_edata ldr r2, =_sidata movs r3, #0 b LoopCopyDataInit CopyDataInit: ldr r4, [r2, r3] str r4, [r0, r3] adds r3, r3, #4 LoopCopyDataInit: adds r4, r0, r3 cmp r4, r1 bcc CopyDataInit /* Zero fill the bss segment. */ ldr r2, =_sbss ldr r4, =_ebss movs r3, #0 b LoopFillZerobss FillZerobss: str r3, [r2] adds r2, r2, #4 LoopFillZerobss: cmp r2, r4 bcc FillZerobss /* Call static constructors */ bl __libc_init_array /* Call the application's entry point.*/ bl main LoopForever: b LoopForever .size Reset_Handler, .-Reset_Handler /** * @brief This is the code that gets called when the processor receives an * unexpected interrupt. This simply enters an infinite loop, preserving * the system state for examination by a debugger. * * @param None * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop .size Default_Handler, .-Default_Handler /****************************************************************************** * * The STM32H743IITx vector table. Note that the proper constructs * must be placed on this to ensure that it ends up at physical address * 0x0000.0000. * ******************************************************************************/ .section .isr_vector,"a",%progbits .type g_pfnVectors, %object .size g_pfnVectors, .-g_pfnVectors g_pfnVectors: .word _estack .word Reset_Handler .word NMI_Handler .word HardFault_Handler .word MemManage_Handler .word BusFault_Handler .word UsageFault_Handler .word 0 .word 0 .word 0 .word 0 .word SVC_Handler .word DebugMon_Handler .word 0 .word PendSV_Handler .word SysTick_Handler .word WWDG1_IRQHandler /* Window Watchdog interrupt */ .word PVD_PVM_IRQHandler /* PVD through EXTI line */ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* RTC tamper, timestamp */ .word RTC_WKUP_IRQHandler /* RTC Wakeup interrupt */ .word FLASH_IRQHandler /* Flash memory */ .word RCC_IRQHandler /* RCC global interrupt */ .word EXTI0_IRQHandler /* EXTI Line 0 interrupt */ .word EXTI1_IRQHandler /* EXTI Line 1 interrupt */ .word EXTI2_IRQHandler /* EXTI Line 2 interrupt */ .word EXTI3_IRQHandler /* EXTI Line 3interrupt */ .word EXTI4_IRQHandler /* EXTI Line 4interrupt */ .word DMA_STR0_IRQHandler /* DMA1 Stream0 */ .word DMA_STR1_IRQHandler /* DMA1 Stream1 */ .word DMA_STR2_IRQHandler /* DMA1 Stream2 */ .word DMA_STR3_IRQHandler /* DMA1 Stream3 */ .word DMA_STR4_IRQHandler /* DMA1 Stream4 */ .word DMA_STR5_IRQHandler /* DMA1 Stream5 */ .word DMA_STR6_IRQHandler /* DMA1 Stream6 */ .word ADC1_2_IRQHandler /* ADC1 and ADC2 */ .word FDCAN1_IT0_IRQHandler /* FDCAN1 Interrupt 0 */ .word FDCAN2_IT0_IRQHandler /* FDCAN2 Interrupt 0 */ .word FDCAN1_IT1_IRQHandler /* FDCAN1 Interrupt 1 */ .word FDCAN2_IT1_IRQHandler /* FDCAN2 Interrupt 1 */ .word EXTI9_5_IRQHandler /* EXTI Line[9:5] interrupts */ .word TIM1_BRK_IRQHandler /* TIM1 break interrupt */ .word TIM1_UP_IRQHandler /* TIM1 update interrupt */ .word TIM1_TRG_COM_IRQHandler /* TIM1 trigger and commutation */ .word TIM_CC_IRQHandler /* TIM1 capture / compare */ .word TIM2_IRQHandler /* TIM2 global interrupt */ .word TIM3_IRQHandler /* TIM3 global interrupt */ .word TIM4_IRQHandler /* TIM4 global interrupt */ .word I2C1_EV_IRQHandler /* I2C1 event interrupt */ .word I2C1_ER_IRQHandler /* I2C1 error interrupt */ .word I2C2_EV_IRQHandler /* I2C2 event interrupt */ .word I2C2_ER_IRQHandler /* I2C2 error interrupt */ .word SPI1_IRQHandler /* SPI1 global interrupt */ .word SPI2_IRQHandler /* SPI2 global interrupt */ .word USART1_IRQHandler /* USART1 global interrupt */ .word USART2_IRQHandler /* USART2 global interrupt */ .word USART3_IRQHandler /* USART3 global interrupt */ .word EXTI15_10_IRQHandler /* EXTI Line[15:10] interrupts */ .word RTC_ALARM_IRQHandler /* RTC alarms (A and B) */ .word 0 /* Reserved */ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 and 12 break global */ .word TIM8_UP_TIM13_IRQHandler /* TIM8 and 13 update global */ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 and 14 trigger /commutation and global */ .word TIM8_CC_IRQHandler /* TIM8 capture / compare */ .word DMA1_STR7_IRQHandler /* DMA1 Stream7 */ .word FMC_IRQHandler /* FMC global interrupt */ .word SDMMC1_IRQHandler /* SDMMC global interrupt */ .word TIM5_IRQHandler /* TIM5 global interrupt */ .word SPI3_IRQHandler /* SPI3 global interrupt */ .word UART4_IRQHandler /* UART4 global interrupt */ .word UART5_IRQHandler /* UART5 global interrupt */ .word TIM6_DAC_IRQHandler /* TIM6 global interrupt */ .word TIM7_IRQHandler /* TIM7 global interrupt */ .word DMA2_STR0_IRQHandler /* DMA2 Stream0 interrupt */ .word DMA2_STR1_IRQHandler /* DMA2 Stream1 interrupt */ .word DMA2_STR2_IRQHandler /* DMA2 Stream2 interrupt */ .word DMA2_STR3_IRQHandler /* DMA2 Stream3 interrupt */ .word DMA2_STR4_IRQHandler /* DMA2 Stream4 interrupt */ .word ETH_IRQHandler /* Ethernet global interrupt */ .word ETH_WKUP_IRQHandler /* Ethernet wakeup through EXTI */ .word FDCAN_CAL_IRQHandler /* CAN2TX interrupts */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word DMA2_STR5_IRQHandler /* DMA2 Stream5 interrupt */ .word DMA2_STR6_IRQHandler /* DMA2 Stream6 interrupt */ .word DMA2_STR7_IRQHandler /* DMA2 Stream7 interrupt */ .word USART6_IRQHandler /* USART6 global interrupt */ .word I2C3_EV_IRQHandler /* I2C3 event interrupt */ .word I2C3_ER_IRQHandler /* I2C3 error interrupt */ .word OTG_HS_EP1_OUT_IRQHandler /* OTG_HS out global interrupt */ .word OTG_HS_EP1_IN_IRQHandler /* OTG_HS in global interrupt */ .word OTG_HS_WKUP_IRQHandler /* OTG_HS wakeup interrupt */ .word OTG_HS_IRQHandler /* OTG_HS global interrupt */ .word DCMI_IRQHandler /* DCMI global interrupt */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word FPU_IRQHandler /* Floating point unit interrupt */ .word UART7_IRQHandler /* UART7 global interrupt */ .word UART8_IRQHandler /* UART8 global interrupt */ .word SPI4_IRQHandler /* SPI4 global interrupt */ .word SPI5_IRQHandler /* SPI5 global interrupt */ .word SPI6_IRQHandler /* SPI6 global interrupt */ .word SAI1_IRQHandler /* SAI1 global interrupt */ .word LTDC_IRQHandler /* LCD-TFT global interrupt */ .word LTDC_ER_IRQHandler /* LCD-TFT error interrupt */ .word DMA2D_IRQHandler /* DMA2D global interrupt */ .word SAI2_IRQHandler /* SAI2 global interrupt */ .word QUADSPI_IRQHandler /* QuadSPI global interrupt */ .word LPTIM1_IRQHandler /* LPTIM1 global interrupt */ .word CEC_IRQHandler /* HDMI-CEC global interrupt */ .word I2C4_EV_IRQHandler /* I2C4 event interrupt */ .word I2C4_ER_IRQHandler /* I2C4 error interrupt */ .word SPDIF_IRQHandler /* SPDIFRX global interrupt */ .word OTG_FS_EP1_OUT_IRQHandler /* OTG_FS out global interrupt */ .word OTG_FS_EP1_IN_IRQHandler /* OTG_FS in global interrupt */ .word OTG_FS_WKUP_IRQHandler /* OTG_FS wakeup */ .word OTG_FS_IRQHandler /* OTG_FS global interrupt */ .word DMAMUX1_OV_IRQHandler /* DMAMUX1 overrun interrupt */ .word HRTIM1_MST_IRQHandler /* HRTIM1 master timer interrupt */ .word HRTIM1_TIMA_IRQHandler /* HRTIM1 timer A interrupt */ .word HRTIM_TIMB_IRQHandler /* HRTIM1 timer B interrupt */ .word HRTIM1_TIMC_IRQHandler /* HRTIM1 timer C interrupt */ .word HRTIM1_TIMD_IRQHandler /* HRTIM1 timer D interrupt */ .word HRTIM_TIME_IRQHandler /* HRTIM1 timer E interrupt */ .word HRTIM1_FLT_IRQHandler /* HRTIM1 fault interrupt */ .word DFSDM1_FLT0_IRQHandler /* DFSDM1 filter 0 interrupt */ .word DFSDM1_FLT1_IRQHandler /* DFSDM1 filter 1 interrupt */ .word DFSDM1_FLT2_IRQHandler /* DFSDM1 filter 2 interrupt */ .word DFSDM1_FLT3_IRQHandler /* DFSDM1 filter 3 interrupt */ .word SAI3_IRQHandler /* SAI3 global interrupt */ .word SWPMI1_IRQHandler /* SWPMI global interrupt */ .word TIM15_IRQHandler /* TIM15 global interrupt */ .word TIM16_IRQHandler /* TIM16 global interrupt */ .word TIM17_IRQHandler /* TIM17 global interrupt */ .word MDIOS_WKUP_IRQHandler /* MDIOS wakeup */ .word MDIOS_IRQHandler /* MDIOS global interrupt */ .word JPEG_IRQHandler /* JPEG global interrupt */ .word MDMA_IRQHandler /* MDMA */ .word 0 /* Reserved */ .word SDMMC_IRQHandler /* SDMMC global interrupt */ .word HSEM0_IRQHandler /* HSEM global interrupt 1 */ .word 0 /* Reserved */ .word ADC3_IRQHandler /* ADC3 global interrupt */ .word DMAMUX2_OVR_IRQHandler /* DMAMUX2 overrun interrupt */ .word BDMA_CH1_IRQHandler /* BDMA channel 1 interrupt */ .word BDMA_CH2_IRQHandler /* BDMA channel 2 interrupt */ .word BDMA_CH3_IRQHandler /* BDMA channel 3 interrupt */ .word BDMA_CH4_IRQHandler /* BDMA channel 4 interrupt */ .word BDMA_CH5_IRQHandler /* BDMA channel 5 interrupt */ .word BDMA_CH6_IRQHandler /* BDMA channel 6 interrupt */ .word BDMA_CH7_IRQHandler /* BDMA channel 7 interrupt */ .word BDMA_CH8_IRQHandler /* BDMA channel 8 interrupt */ .word COMP_IRQHandler /* COMP1 and COMP2 */ .word LPTIM2_IRQHandler /* LPTIM2 timer interrupt */ .word LPTIM3_IRQHandler /* LPTIM2 timer interrupt */ .word LPTIM4_IRQHandler /* LPTIM2 timer interrupt */ .word LPTIM5_IRQHandler /* LPTIM2 timer interrupt */ .word LPUART_IRQHandler /* LPUART global interrupt */ .word WWDG1_RST_IRQHandler /* Window Watchdog interrupt */ .word CRS_IRQHandler /* Clock Recovery System globa */ .word 0 /* Reserved */ .word SAI4_IRQHandler /* SAI4 global interrupt */ .word 0 /* Reserved */ .word 0 /* Reserved */ .word WKUP_IRQHandler /* WKUP1 to WKUP6 pins */ /******************************************************************************* * * Provide weak aliases for each Exception handler to the Default_Handler. * As they are weak aliases, any function with the same name will override * this definition. * *******************************************************************************/ .weak NMI_Handler .thumb_set NMI_Handler,Default_Handler .weak HardFault_Handler .thumb_set HardFault_Handler,Default_Handler .weak MemManage_Handler .thumb_set MemManage_Handler,Default_Handler .weak BusFault_Handler .thumb_set BusFault_Handler,Default_Handler .weak UsageFault_Handler .thumb_set UsageFault_Handler,Default_Handler .weak SVC_Handler .thumb_set SVC_Handler,Default_Handler .weak DebugMon_Handler .thumb_set DebugMon_Handler,Default_Handler .weak PendSV_Handler .thumb_set PendSV_Handler,Default_Handler .weak SysTick_Handler .thumb_set SysTick_Handler,Default_Handler .weak WWDG1_IRQHandler .thumb_set WWDG1_IRQHandler,Default_Handler .weak PVD_PVM_IRQHandler .thumb_set PVD_PVM_IRQHandler,Default_Handler .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler .weak RTC_WKUP_IRQHandler .thumb_set RTC_WKUP_IRQHandler,Default_Handler .weak FLASH_IRQHandler .thumb_set FLASH_IRQHandler,Default_Handler .weak RCC_IRQHandler .thumb_set RCC_IRQHandler,Default_Handler .weak EXTI0_IRQHandler .thumb_set EXTI0_IRQHandler,Default_Handler .weak EXTI1_IRQHandler .thumb_set EXTI1_IRQHandler,Default_Handler .weak EXTI2_IRQHandler .thumb_set EXTI2_IRQHandler,Default_Handler .weak EXTI3_IRQHandler .thumb_set EXTI3_IRQHandler,Default_Handler .weak EXTI4_IRQHandler .thumb_set EXTI4_IRQHandler,Default_Handler .weak DMA_STR0_IRQHandler .thumb_set DMA_STR0_IRQHandler,Default_Handler .weak DMA_STR1_IRQHandler .thumb_set DMA_STR1_IRQHandler,Default_Handler .weak DMA_STR2_IRQHandler .thumb_set DMA_STR2_IRQHandler,Default_Handler .weak DMA_STR3_IRQHandler .thumb_set DMA_STR3_IRQHandler,Default_Handler .weak DMA_STR4_IRQHandler .thumb_set DMA_STR4_IRQHandler,Default_Handler .weak DMA_STR5_IRQHandler .thumb_set DMA_STR5_IRQHandler,Default_Handler .weak DMA_STR6_IRQHandler .thumb_set DMA_STR6_IRQHandler,Default_Handler .weak ADC1_2_IRQHandler .thumb_set ADC1_2_IRQHandler,Default_Handler .weak FDCAN1_IT0_IRQHandler .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler .weak FDCAN2_IT0_IRQHandler .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler .weak FDCAN1_IT1_IRQHandler .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler .weak FDCAN2_IT1_IRQHandler .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler .weak EXTI9_5_IRQHandler .thumb_set EXTI9_5_IRQHandler,Default_Handler .weak TIM1_BRK_IRQHandler .thumb_set TIM1_BRK_IRQHandler,Default_Handler .weak TIM1_UP_IRQHandler .thumb_set TIM1_UP_IRQHandler,Default_Handler .weak TIM1_TRG_COM_IRQHandler .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler .weak TIM_CC_IRQHandler .thumb_set TIM_CC_IRQHandler,Default_Handler .weak TIM2_IRQHandler .thumb_set TIM2_IRQHandler,Default_Handler .weak TIM3_IRQHandler .thumb_set TIM3_IRQHandler,Default_Handler .weak TIM4_IRQHandler .thumb_set TIM4_IRQHandler,Default_Handler .weak I2C1_EV_IRQHandler .thumb_set I2C1_EV_IRQHandler,Default_Handler .weak I2C1_ER_IRQHandler .thumb_set I2C1_ER_IRQHandler,Default_Handler .weak I2C2_EV_IRQHandler .thumb_set I2C2_EV_IRQHandler,Default_Handler .weak I2C2_ER_IRQHandler .thumb_set I2C2_ER_IRQHandler,Default_Handler .weak SPI1_IRQHandler .thumb_set SPI1_IRQHandler,Default_Handler .weak SPI2_IRQHandler .thumb_set SPI2_IRQHandler,Default_Handler .weak USART1_IRQHandler .thumb_set USART1_IRQHandler,Default_Handler .weak USART2_IRQHandler .thumb_set USART2_IRQHandler,Default_Handler .weak USART3_IRQHandler .thumb_set USART3_IRQHandler,Default_Handler .weak EXTI15_10_IRQHandler .thumb_set EXTI15_10_IRQHandler,Default_Handler .weak RTC_ALARM_IRQHandler .thumb_set RTC_ALARM_IRQHandler,Default_Handler .weak TIM8_BRK_TIM12_IRQHandler .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler .weak TIM8_UP_TIM13_IRQHandler .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler .weak TIM8_TRG_COM_TIM14_IRQHandler .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler .weak TIM8_CC_IRQHandler .thumb_set TIM8_CC_IRQHandler,Default_Handler .weak DMA1_STR7_IRQHandler .thumb_set DMA1_STR7_IRQHandler,Default_Handler .weak FMC_IRQHandler .thumb_set FMC_IRQHandler,Default_Handler .weak SDMMC1_IRQHandler .thumb_set SDMMC1_IRQHandler,Default_Handler .weak TIM5_IRQHandler .thumb_set TIM5_IRQHandler,Default_Handler .weak SPI3_IRQHandler .thumb_set SPI3_IRQHandler,Default_Handler .weak UART4_IRQHandler .thumb_set UART4_IRQHandler,Default_Handler .weak UART5_IRQHandler .thumb_set UART5_IRQHandler,Default_Handler .weak TIM6_DAC_IRQHandler .thumb_set TIM6_DAC_IRQHandler,Default_Handler .weak TIM7_IRQHandler .thumb_set TIM7_IRQHandler,Default_Handler .weak DMA2_STR0_IRQHandler .thumb_set DMA2_STR0_IRQHandler,Default_Handler .weak DMA2_STR1_IRQHandler .thumb_set DMA2_STR1_IRQHandler,Default_Handler .weak DMA2_STR2_IRQHandler .thumb_set DMA2_STR2_IRQHandler,Default_Handler .weak DMA2_STR3_IRQHandler .thumb_set DMA2_STR3_IRQHandler,Default_Handler .weak DMA2_STR4_IRQHandler .thumb_set DMA2_STR4_IRQHandler,Default_Handler .weak ETH_IRQHandler .thumb_set ETH_IRQHandler,Default_Handler .weak ETH_WKUP_IRQHandler .thumb_set ETH_WKUP_IRQHandler,Default_Handler .weak FDCAN_CAL_IRQHandler .thumb_set FDCAN_CAL_IRQHandler,Default_Handler .weak DMA2_STR5_IRQHandler .thumb_set DMA2_STR5_IRQHandler,Default_Handler .weak DMA2_STR6_IRQHandler .thumb_set DMA2_STR6_IRQHandler,Default_Handler .weak DMA2_STR7_IRQHandler .thumb_set DMA2_STR7_IRQHandler,Default_Handler .weak USART6_IRQHandler .thumb_set USART6_IRQHandler,Default_Handler .weak I2C3_EV_IRQHandler .thumb_set I2C3_EV_IRQHandler,Default_Handler .weak I2C3_ER_IRQHandler .thumb_set I2C3_ER_IRQHandler,Default_Handler .weak OTG_HS_EP1_OUT_IRQHandler .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_HS_EP1_IN_IRQHandler .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler .weak OTG_HS_WKUP_IRQHandler .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler .weak OTG_HS_IRQHandler .thumb_set OTG_HS_IRQHandler,Default_Handler .weak DCMI_IRQHandler .thumb_set DCMI_IRQHandler,Default_Handler .weak FPU_IRQHandler .thumb_set FPU_IRQHandler,Default_Handler .weak UART7_IRQHandler .thumb_set UART7_IRQHandler,Default_Handler .weak UART8_IRQHandler .thumb_set UART8_IRQHandler,Default_Handler .weak SPI4_IRQHandler .thumb_set SPI4_IRQHandler,Default_Handler .weak SPI5_IRQHandler .thumb_set SPI5_IRQHandler,Default_Handler .weak SPI6_IRQHandler .thumb_set SPI6_IRQHandler,Default_Handler .weak SAI1_IRQHandler .thumb_set SAI1_IRQHandler,Default_Handler .weak LTDC_IRQHandler .thumb_set LTDC_IRQHandler,Default_Handler .weak LTDC_ER_IRQHandler .thumb_set LTDC_ER_IRQHandler,Default_Handler .weak DMA2D_IRQHandler .thumb_set DMA2D_IRQHandler,Default_Handler .weak SAI2_IRQHandler .thumb_set SAI2_IRQHandler,Default_Handler .weak QUADSPI_IRQHandler .thumb_set QUADSPI_IRQHandler,Default_Handler .weak LPTIM1_IRQHandler .thumb_set LPTIM1_IRQHandler,Default_Handler .weak CEC_IRQHandler .thumb_set CEC_IRQHandler,Default_Handler .weak I2C4_EV_IRQHandler .thumb_set I2C4_EV_IRQHandler,Default_Handler .weak I2C4_ER_IRQHandler .thumb_set I2C4_ER_IRQHandler,Default_Handler .weak SPDIF_IRQHandler .thumb_set SPDIF_IRQHandler,Default_Handler .weak OTG_FS_EP1_OUT_IRQHandler .thumb_set OTG_FS_EP1_OUT_IRQHandler,Default_Handler .weak OTG_FS_EP1_IN_IRQHandler .thumb_set OTG_FS_EP1_IN_IRQHandler,Default_Handler .weak OTG_FS_WKUP_IRQHandler .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler .weak OTG_FS_IRQHandler .thumb_set OTG_FS_IRQHandler,Default_Handler .weak DMAMUX1_OV_IRQHandler .thumb_set DMAMUX1_OV_IRQHandler,Default_Handler .weak HRTIM1_MST_IRQHandler .thumb_set HRTIM1_MST_IRQHandler,Default_Handler .weak HRTIM1_TIMA_IRQHandler .thumb_set HRTIM1_TIMA_IRQHandler,Default_Handler .weak HRTIM_TIMB_IRQHandler .thumb_set HRTIM_TIMB_IRQHandler,Default_Handler .weak HRTIM1_TIMC_IRQHandler .thumb_set HRTIM1_TIMC_IRQHandler,Default_Handler .weak HRTIM1_TIMD_IRQHandler .thumb_set HRTIM1_TIMD_IRQHandler,Default_Handler .weak HRTIM_TIME_IRQHandler .thumb_set HRTIM_TIME_IRQHandler,Default_Handler .weak HRTIM1_FLT_IRQHandler .thumb_set HRTIM1_FLT_IRQHandler,Default_Handler .weak DFSDM1_FLT0_IRQHandler .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler .weak DFSDM1_FLT1_IRQHandler .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler .weak DFSDM1_FLT2_IRQHandler .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler .weak DFSDM1_FLT3_IRQHandler .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler .weak SAI3_IRQHandler .thumb_set SAI3_IRQHandler,Default_Handler .weak SWPMI1_IRQHandler .thumb_set SWPMI1_IRQHandler,Default_Handler .weak TIM15_IRQHandler .thumb_set TIM15_IRQHandler,Default_Handler .weak TIM16_IRQHandler .thumb_set TIM16_IRQHandler,Default_Handler .weak TIM17_IRQHandler .thumb_set TIM17_IRQHandler,Default_Handler .weak MDIOS_WKUP_IRQHandler .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler .weak MDIOS_IRQHandler .thumb_set MDIOS_IRQHandler,Default_Handler .weak JPEG_IRQHandler .thumb_set JPEG_IRQHandler,Default_Handler .weak MDMA_IRQHandler .thumb_set MDMA_IRQHandler,Default_Handler .weak SDMMC_IRQHandler .thumb_set SDMMC_IRQHandler,Default_Handler .weak HSEM0_IRQHandler .thumb_set HSEM0_IRQHandler,Default_Handler .weak ADC3_IRQHandler .thumb_set ADC3_IRQHandler,Default_Handler .weak DMAMUX2_OVR_IRQHandler .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler .weak BDMA_CH1_IRQHandler .thumb_set BDMA_CH1_IRQHandler,Default_Handler .weak BDMA_CH2_IRQHandler .thumb_set BDMA_CH2_IRQHandler,Default_Handler .weak BDMA_CH3_IRQHandler .thumb_set BDMA_CH3_IRQHandler,Default_Handler .weak BDMA_CH4_IRQHandler .thumb_set BDMA_CH4_IRQHandler,Default_Handler .weak BDMA_CH5_IRQHandler .thumb_set BDMA_CH5_IRQHandler,Default_Handler .weak BDMA_CH6_IRQHandler .thumb_set BDMA_CH6_IRQHandler,Default_Handler .weak BDMA_CH7_IRQHandler .thumb_set BDMA_CH7_IRQHandler,Default_Handler .weak BDMA_CH8_IRQHandler .thumb_set BDMA_CH8_IRQHandler,Default_Handler .weak COMP_IRQHandler .thumb_set COMP_IRQHandler,Default_Handler .weak LPTIM2_IRQHandler .thumb_set LPTIM2_IRQHandler,Default_Handler .weak LPTIM3_IRQHandler .thumb_set LPTIM3_IRQHandler,Default_Handler .weak LPTIM4_IRQHandler .thumb_set LPTIM4_IRQHandler,Default_Handler .weak LPTIM5_IRQHandler .thumb_set LPTIM5_IRQHandler,Default_Handler .weak LPUART_IRQHandler .thumb_set LPUART_IRQHandler,Default_Handler .weak WWDG1_RST_IRQHandler .thumb_set WWDG1_RST_IRQHandler,Default_Handler .weak CRS_IRQHandler .thumb_set CRS_IRQHandler,Default_Handler .weak SAI4_IRQHandler .thumb_set SAI4_IRQHandler,Default_Handler .weak WKUP_IRQHandler .thumb_set WKUP_IRQHandler,Default_Handler .weak SystemInit /************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/ Вообще, у меня дерево и состав проекта сейчас такой (там более-менее стандартные хедеры и пр.): 10 минут назад, jcxz сказал: 7. Отделить мух от котлет определить в чём именно проблема: с вызовом ISR или настройкой таймера? Для чего использовать соответствующие регистры NVIC (для просмотра статуса ожидающего прерывания и для программного возбуждения прерывания). Попробую разобраться тут, но пока что не очень получается и поэтому спросил тут, но я еще попробую. Спасибо. Добавлю - весь код "InitSystemMCU.c" я уже приводил (в самом 1-ом посту - "скрытый текст"). Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
jcxz 184 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 4 минуты назад, AleksBak сказал: Это все вроде происходит в коде (извините про него забыл привести инф-цию) - "startup_stm32h743iitx.s" "вроде" - ключевое слово... Гадать по "дереву проекта" не умею. Предпочитаю проверять по .map-файлу и при помощи J-Link/ST-Link. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 4 минуты назад, jcxz сказал: "вроде" - ключевое слово... Да конечно. 4 минуты назад, jcxz сказал: Гадать по "дереву проекта" не умею. Предпочитаю проверять по .map-файлу и при помощи J-Link/ST-Link. Спасибо большое за помощь. Вот содержимое "H7_L01_QSPI.map" этого проекта (я ничтожный хотел выделить красным некоторые места тут - но покамест не получилось): Скрытый текст Archive member included to satisfy reference by file (symbol) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-errno.o) Src/syscalls.o (__errno) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-exit.o) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/crt0.o (exit) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-impure.o) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-exit.o) (_global_impure_ptr) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-init.o) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard/crt0.o (__libc_init_array) c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-memset.o) 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0x000000000000007b 0x7c Src/main.o .debug_frame 0x0000000000000000 0x1a4 .debug_frame 0x0000000000000000 0x58 CMSIS/Src/system_stm32h7xx.o .debug_frame 0x0000000000000058 0x80 Src/InitSystemMCU.o .debug_frame 0x00000000000000d8 0xa0 Src/main.o .debug_frame 0x0000000000000178 0x2c c:/st/stm32cubeide_1.0.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv5/hard\libc_nano.a(lib_a-init.o) Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
haker_fox 60 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 26 minutes ago, jcxz said: Для чего использовать соответствующие регистры NVIC (для просмотра статуса ожидающего прерывания и для программного возбуждения прерывания). Точно! Автор темы, вы можете возбудить прерывание только в NVIC, свою периферию можете даже и не включать. Используйте это) Мне иногда помогало, когда искал ошибки в ПО у своих коллег. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
HardEgor 65 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 9 минут назад, AleksBak сказал: Попробую разобраться тут, но пока что не очень получается и поэтому спросил тут, но я еще попробую. Спасибо. В отладчике в NVIC смотрите есть ли флаг Active и Pending на вашем прерывание. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 35 минут назад, jcxz сказал: 6. Прописать соответствующий вектор таблицы прерываний на нужный ISR. Оно похоже это и не происходит все-таки как раз тут - см. этот map-файл. @jcxz - Вы вроде правы. Еще надо подумать тут (мне). 9 минут назад, haker_fox сказал: Автор темы, вы можете возбудить прерывание только в NVIC, свою периферию можете даже и не включать. Используйте это) Сейчас попробую Покамест не очень понял как, но начну пробовать. 10 минут назад, HardEgor сказал: В отладчике в NVIC смотрите есть ли флаг Active и Pending на вашем прерывание. Тоже сейчас попробую (минут через 10-15). Спасибо за помощь. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
haker_fox 60 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 3 minutes ago, AleksBak said: Сейчас попробую Покамест не очень понял как, но начну пробовать. Только точку останова поставьте в таблице на нужный адрес. Чтобы точно увидеть есть ли прерывание. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 13 минут назад, HardEgor сказал: В отладчике в NVIC смотрите есть ли флаг Active и Pending на вашем прерывание. Добавлю - я пока сейчас поищу инф-цию/поизучаю, то как все-таки надо прописать вектора таблицы на нужный ISR - как @jcxz заметил, а потом в отладке буду ковыряться. Спасибо Вам. Похоже проблема тут у меня. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
haker_fox 60 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 3 minutes ago, AleksBak said: а потом в отладке буду ковыряться. Как раз быстрее с отладчиком. Жмакнули бряк, и... видим результат. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
jcxz 184 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 36 минут назад, AleksBak сказал: Спасибо большое за помощь. Вот содержимое "H7_L01_QSPI.map" этого проекта (я ничтожный хотел выделить красным некоторые места тут - но покамест не получилось): По .map-файлу видно что: 1. Ваш ISR не используется при линковке программы. Так как строчка: .text.TIM2_IRQhandler 0x0000000000000000 0x3c Src/main.o говорит о том, что его адресу присвоено значение ==0. 2. А строки: .text.Default_Handler ... 0x0000000008000f78 TIM2_IRQHandler ... говорят о том, что на место данного вектора вставляется адрес некоей функции-заглушки Default_Handler() (для неиспользуемых векторов прерываний видимо). Которая берётся из той кучи хлама чужого кода, которую вы подключили к проекту. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
AleksBak 0 16 октября, 2020 Опубликовано 16 октября, 2020 · Жалоба 9 минут назад, jcxz сказал: По .map-файлу видно что: 1. Ваш ISR не используется при линковке программы. Так как строчка: Уважаемый @jcxz Вам бы снайпером пойти служить спокойно можно т.к. точно указали (также как и другие тут на др. причины). Я уже понял это после того как привел, по Вашему указанию, map файл тут и стал изучать его хотя бы немного. Спасибо Вам по человечески. Я сейчас должен пойти/прийти по одному делу и чуть позже начну разбираться опять. 16 минут назад, jcxz сказал: Которая берётся из той кучи хлама чужого кода, которую вы подключили к проекту Согласен насчет чужого и нехорошего, но и это всего лишь 1-2% от кубического проповедения. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
