digger2024 0 1 февраля Опубликовано 1 февраля · Жалоба Здравствуйте! Возникла проблема при настройке кодека TLV320AIC3204 + STM. Регистры пишутся и читаются по I2C без проблем, MCLK от МК, в байпас режиме сигнал от микрофонов проходит до выходов без проблем, но в digital loopback сигнала на выходе нет, проверка регистров ничего не дала, очень похоже, что не настраиваться Clock для АЦП и ЦАП, хотя все делаю по руководству. PLL не используется. wait(5); /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, PAGE_SELEC, 0); /* Software reset AIC3204 */ AIC3204_I2C_WriteRegister(handle, SOFT_RESET, 1); /***************************************************** * PROGRAM CLOCK SETTINGS * Set DAC configuration * Set ADC configuration *****************************************************/ /*Set ADC configuration */ /* Set up the NADC divider with value */ AIC3204_I2C_WriteRegister(handle, CLOCK_SETTING_R8, NADC_ON|NADC_DIV); /* Set up the MADC divider with value */ AIC3204_I2C_WriteRegister(handle, CLOCK_SETTING_R9, MADC_ON|MADC_DIV); /* Set up the ADCOSR with value */ AIC3204_I2C_WriteRegister(handle, ADC_OSR_R, ADC_OSR_DIV); /* Select the ADC Mode */ AIC3204_I2C_WriteRegister(handle, ASPB_CTRL_R, ADC_MODE); /* Set DAC configuration */ /* Set up the NDAC divider with value */ AIC3204_I2C_WriteRegister(handle, CLOCK_SETTING_R6, NDAC_ON|NDAC_DIV); /* Set up the MDAC divider with value */ AIC3204_I2C_WriteRegister(handle, CLOCK_SETTING_R7, MDAC_ON|MDAC_DIV); /* Set up the DACOSR with value */ AIC3204_I2C_WriteRegister(handle, DAC_OSR_1, DAC_OSR_DIV>>8); AIC3204_I2C_WriteRegister(handle, DAC_OSR_2, 0xFF&DAC_OSR_DIV); /*Sets AI = I2S, Data Word length = 20bit, BCLK is input, WCLK is input, DOUT will be high impedance after data has been transferred*/ AIC3204_I2C_WriteRegister(handle, AI_SETTING_R1, AI_SETTING_R1_Config); //AIC3204_I2C_WriteRegister(handle, AI_SETTING_R6, AI_SETTING_R6_Config); /* Select the DAC Mode */ AIC3204_I2C_WriteRegister(handle, DSPB_CTRL_R, DAC_MODE); /************************************************ * * PROGRAM ANALOG BLOCKS * ************************************************/ /* Select Page 1 */ AIC3204_I2C_WriteRegister(handle, PAGE_SELEC, 1); /*Set ADC configuration continue ... */ /*Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO */ AIC3204_I2C_WriteRegister(handle, POWER_CONF_R, 0x08); /* Enable Master Analog Power Control */ AIC3204_I2C_WriteRegister(handle, LDO_CTRL_R, LDO_AB_EN); /* Set the input common mode */ AIC3204_I2C_WriteRegister(handle, COM_MODE_CTRL_R, INPUT_COM_MODE); /* Select ADC Power Tune Mode*/ AIC3204_I2C_WriteRegister(handle, ADC_POW_TUNE_CONF_R, ADC_PTM); /* Set MicPGA startup delay */ AIC3204_I2C_WriteRegister(handle, AINPUT_QCHARG_CONF_F_R, MICPGA_STARTUP_TIME); /* Set the REF charging time */ AIC3204_I2C_WriteRegister(handle, REF_POWER_UP_CONF_R, REF_CHARGING_TIME); /*Set MICPGA configuration */ /* Route IN1L to LEFT_P with 10K input impedance*/ AIC3204_I2C_WriteRegister(handle, MICPGA_LP_ROUT_CONF_R, MICPGA_LP_ROUT_CONF); /* Route Common Mode to LEFT_M with impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, MICPGA_LN_ROUT_CONF_R, MICPGA_LN_ROUT_CONF); /* Route IN1R to RIGHT_P with input impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, MICPGA_RP_ROUT_CONF_R, MICPGA_RP_ROUT_CONF); /* Route Common Mode to RIGHT_M with impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, MICPGA_RN_ROUT_CONF_R, MICPGA_RN_ROUT_CONF); /* Unmute Left MICPGA & set volume*/ AIC3204_I2C_WriteRegister(handle, MICPGA_L_VOL_CTRL_R, MICPGA_L_VOL_CTRL); /* Unmute Right MICPGA & set volume*/ AIC3204_I2C_WriteRegister(handle, MICPGA_R_VOL_CTRL_R, MICPGA_R_VOL_CTRL); /* Power up MICBIAS * MICBIAS voltage is generated from AVDD & Power up MICBIAS with 2.045V (else AVDD if from AVDD) */ AIC3204_I2C_WriteRegister(handle, MICBIAS_CONF_R, MICBIAS_CONF); /********************************************************************* * * POWER UP ADC * ********************************************************************/ /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, PAGE_SELEC, 0); /* Power up Left and Right ADC Channels */ AIC3204_I2C_WriteRegister(handle, ADC_CHAN_SET_R, POW_UP_R_ADC_C|POW_UP_L_ADC_C); /* Unmute Left and Right ADC Digital Volume Control. */ AIC3204_I2C_WriteRegister(handle, ADC_FINE_GAIN_R, 0); /******************************************************************* * * PLAYBACK SETUP * ******************************************************************/ /* Select Page 1 */ AIC3204_I2C_WriteRegister(handle, PAGE_SELEC, 1); /* HP soft stepping settings for optimal pop performance at power up * Rpop used is 6k with N = 6 and soft step = 0 */ AIC3204_I2C_WriteRegister(handle, HP_DRIVER_STARTUP_R, 0x25); /*Route Left DAC to HPL*/ AIC3204_I2C_WriteRegister(handle, HPL_ROUT_SEL_R, HPL_ROUT); /*Route Right DAC to HPR*/ AIC3204_I2C_WriteRegister(handle, HPR_ROUT_SEL_R, HPR_ROUT); /* Set the DAC PTM mode to PTM_P1 */ AIC3204_I2C_WriteRegister(handle, PB_CONF_R1, DAC_PTM); AIC3204_I2C_WriteRegister(handle, PB_CONF_R2, DAC_PTM); /* Power up HPL and HPR drivers */ AIC3204_I2C_WriteRegister(handle, OUT_DRIVER_CTRL_R, OUT_DRIVER_CTRL); /* Unmute HPL driver */ AIC3204_I2C_WriteRegister(handle, HPL_DRIVER_GAIN_R, HPL_DRIVER_GAIN); /* Unmute HPR driver */ AIC3204_I2C_WriteRegister(handle, HPR_DRIVER_GAIN_R, HPR_DRIVER_GAIN); AIC3204_I2C_WriteRegister(handle, LOL_DRIVER_GAIN_R, HPR_DRIVER_GAIN); /* Unmute HPR driver */ AIC3204_I2C_WriteRegister(handle, LOR_DRIVER_GAIN_R, HPR_DRIVER_GAIN); //Wait for 2.5 sec for soft stepping to take effect wait(2500); /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, PAGE_SELEC, 0); /* Set up RDAC & up LDAC Initial Volume */ AIC3204_I2C_WriteRegister(handle, LDAC_DVOL_CTRL_R, 0); AIC3204_I2C_WriteRegister(handle, RDAC_DVOL_CTRL_R, 0); /* Power up LR DAC & LR ADC channels */ /* Power up the Left and Right DAC Channels with route the Left Audio digital data to Left Channel DAC and Right Audio digital data to Right Channel DAC */ AIC3204_I2C_WriteRegister(handle, DAC_SETUP_R1, LDAC_ON|RDAC_ON|LDAC_TO_LAID|RDAC_TO_RAID|0x02); /*Left Channel Volume is controlled by Right Channel Volume Control setting Right DAC Channel unmuted Left DAC Channel unmuted Auto Mute disabled When Right DAC Channel is powered down, the data is zero. */ AIC3204_I2C_WriteRegister(handle, DAC_SETUP_R2, 0x01); /* When Right DAC Channel is powered down, the data is zero. b7 = 0 Auto Mute disabled b6-b4 = 000 Right DAC Channel not muted b3 = 0 Left DAC Channel not muted b2 = 0 Left Channel Volume is controlled by Right Channel Volume Control setting b1-b0 = 01 */ /* Sets Audio Bus Loopback, Digital Loopback, Bit Clock Polarity, BCLK and WCLK buffers Power Control, Bit Clock Divider Source */ AIC3204_I2C_WriteRegister(handle, AI_SETTING_R3, AI_SETTING_R3_Config); // Stereo ADC output is routed to Stereo DAC input С некоторые ми изменениями код повторяет следующий скрипт: ############################################### # Software Reset ############################################### # # Select Page 0 w 30 00 00 # # Initialize the device through software reset w 30 01 01 # ############################################### ############################################### # Clock Settings # --------------------------------------------- # The codec receives: MCLK = 11.2896 MHz, # BLCK = 2.8224 MHz, WCLK = 44.1 kHz ############################################### # # Select Page 0 w 30 00 00 # # NADC = 1, MADC = 2 w 30 12 81 82 # ############################################### # # Select Page 0 w 30 00 00 # # NDAC = 1, MDAC = 2 w 30 0b 81 82 # ############################################### ############################################### # Signal Processing Settings ############################################### # # Select Page 0 w 30 00 00 # # Set the ADC Mode to PRB_P1 w 30 3d 01 # # Set the DAC Mode to PRB_P8 w 30 3c 08 # ############################################### ############################################### # Initialize Codec ############################################### # # Select Page 1 w 30 00 01 # # Disable weak AVDD in presence of external # AVDD supply w 30 01 08 # # Enable Master Analog Power Control w 30 02 00 # # Select ADC PTM_R4 w 30 3d 00 # # Set the input powerup time to 3.1ms (for ADC) w 30 47 32 # # Set the REF charging time to 40ms w 30 7b 01 # ############################################### ############################################### # Recording Setup ############################################### # # Select Page 1 w 30 00 01 # # Route IN3L to LEFT_P with 20K input impedance w 30 34 08 # # Route CM1L to LEFT_M with 20K input impedance w 30 36 80 # # Route IN3R to RIGHT_P with 20K input impedance w 30 37 08 # # Route CM1R to RIGHT_M with 20K input impedance w 30 39 80 # # Unmute Left MICPGA, Gain selection of 6dB to make channel gain 0dB # Register of 6dB with input impedance of 20K => Channel Gain of 0dB w 30 3b 0c # # Unmute Right MICPGA, Gain selection of 6dB to make channel gain 0dB # Register of 6dB with input impedance of 20K => Channel Gain of 0dB w 30 3c 0c # # Select Page 0 w 30 00 00 # # Power up LADC/RADC w 30 51 c0 # # Unmute LADC/RADC w 30 52 00 # ############################################### # Playback Setup ############################################### # # Select Page 1 w 30 00 01 # # De-pop w 30 14 25 # # Route LDAC/RDAC to HPL/HPR w 30 0c 08 08 # # Route LDAC/RDAC to LOL/LOR w 30 0e 08 08 # # Power up HPL/HPR and LOL/LOR drivers w 30 09 3C # # Unmute HPL/HPR driver, 0dB Gain w 30 10 00 00 # # Unmute LOL/LOR driver, 0dB Gain w 30 12 00 00 # # Select Page 0 w 30 00 00 # # DAC => 0dB w 30 41 00 00 # # Power up LDAC/RDAC w 30 3f d6 # # Unmute LDAC/RDAC w 30 40 00 # # Page 0 w 30 00 00 # # Digital loopback w 30 1D 10 # ############################################### Подозреваю на проблему с тактирование АЦП и ЦАП, но не могу понять почему. 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digger2024 0 2 февраля Опубликовано 2 февраля · Жалоба /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, 0, 0); /* Software reset AIC3204 */ AIC3204_I2C_WriteRegister(handle, 1, 1); /***************************************************** * PROGRAM CLOCK SETTINGS * Set DAC configuration * Set ADC configuration *****************************************************/ /*Set ADC configuration */ /* Set up the NADC divider with value */ AIC3204_I2C_WriteRegister(handle, 0x12, 0x81); /* Set up the MADC divider with value */ AIC3204_I2C_WriteRegister(handle, 0x13,0x82); /* Set up the ADCOSR with value */ //AIC3204_I2C_WriteRegister(handle, 0x14, 0x80); //Set DAC configuration //Set up the NDAC divider with value AIC3204_I2C_WriteRegister(handle, 0x0B, 0x81); //Set up the MDAC divider with value AIC3204_I2C_WriteRegister(handle, 0x0c, 0x82); /* Select the ADC Mode */ AIC3204_I2C_WriteRegister(handle, 0x3d, 0x01); /*Select the DAC Mode*/ AIC3204_I2C_WriteRegister(handle, 0x3c,0x08); /************************************************ * * PROGRAM ANALOG BLOCKS * ************************************************/ /* Select Page 1 */ AIC3204_I2C_WriteRegister(handle, 0x00, 0x01); /*Set ADC configuration continue ... */ /*Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO */ AIC3204_I2C_WriteRegister(handle, 0x01, 0x08); /* Enable Master Analog Power Control */ AIC3204_I2C_WriteRegister(handle, 0x02, 0x00); /* Select ADC Power Tune Mode*/ AIC3204_I2C_WriteRegister(handle, 0x3d, 0x00); /* Set MicPGA startup delay */ AIC3204_I2C_WriteRegister(handle, 0x47, 0x32); /* Set the REF charging time */ AIC3204_I2C_WriteRegister(handle, 0x7b, 0x01); /*Set MICPGA configuration */ /* Route IN1L to LEFT_P with 10K input impedance*/ AIC3204_I2C_WriteRegister(handle, 0x34, 0x40); /* Route Common Mode to LEFT_M with impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, 0x36, 0x40); /* Route IN1R to RIGHT_P with input impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, 0x37, 0x40); /* Route Common Mode to RIGHT_M with impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, 0x39, 0x40); /* Unmute Left MICPGA & set volume*/ AIC3204_I2C_WriteRegister(handle, 0x3b, 0x0c); /* Unmute Right MICPGA & set volume*/ AIC3204_I2C_WriteRegister(handle, MICPGA_R_VOL_CTRL_R, 0x0c); /* Power up MICBIAS * MICBIAS voltage is generated from AVDD & Power up MICBIAS with 2.045V (else AVDD if from AVDD) */ AIC3204_I2C_WriteRegister(handle, 0x33, 0x60); /********************************************************************* * * POWER UP ADC * ********************************************************************/ /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, 0x00, 0x00); /* Power up Left and Right ADC Channels */ AIC3204_I2C_WriteRegister(handle, 0x51, 0xc0); /* Unmute Left and Right ADC Digital Volume Control. */ AIC3204_I2C_WriteRegister(handle, 0x52, 0x00); /******************************************************************* * * PLAYBACK SETUP * ******************************************************************/ /* Select Page 1*/ AIC3204_I2C_WriteRegister(handle, 0x00, 0x01); /* HP soft stepping settings for optimal pop performance at power up * Rpop used is 6k with N = 6 and soft step = 0*/ AIC3204_I2C_WriteRegister(handle, 0x14, 0x25); /*Route Left DAC to HPL*/ AIC3204_I2C_WriteRegister(handle, 0x0c, 0x08); /*Route Right DAC to HPR*/ AIC3204_I2C_WriteRegister(handle, 0x0d, 0x08); AIC3204_I2C_WriteRegister(handle, 0x0e, 0x08); /*Route Right DAC to HPR*/ AIC3204_I2C_WriteRegister(handle, 0x0f, 0x08); /* Power up HPL and HPR drivers*/ AIC3204_I2C_WriteRegister(handle, 0x09, 0x3c); /* Unmute HPL driver*/ AIC3204_I2C_WriteRegister(handle, 0x10, 0x00); /* Unmute HPR driver*/ AIC3204_I2C_WriteRegister(handle, 0x11, 0x00); AIC3204_I2C_WriteRegister(handle, 0x12, 0x00); /* Unmute HPR driver*/ AIC3204_I2C_WriteRegister(handle, 0x13, 0x00); //Wait for 2.5 sec for soft stepping to take effect //wait(2500); /* Select Page 0*/ AIC3204_I2C_WriteRegister(handle, 0x00, 0x00); /* Set up RDAC & up LDAC Initial Volume*/ AIC3204_I2C_WriteRegister(handle, 0x41, 0x00); AIC3204_I2C_WriteRegister(handle, 0x42, 0x00); /* Power up LR DAC & LR ADC channels*/ /* Power up the Left and Right DAC Channels with route the Left Audio digital data to Left Channel DAC and Right Audio digital data to Right Channel DAC*/ AIC3204_I2C_WriteRegister(handle, 0x3f, 0xd6); /* Sets Audio Bus Loopback, Digital Loopback, Bit Clock Polarity, BCLK and WCLK buffers Power Control, Bit Clock Divider Source*/ AIC3204_I2C_WriteRegister(handle, 0x1d, 0x10); // Stereo ADC output is routed to Stereo DAC input } Собственно реализация последнего скрипта в коде для STM32. Для тактирования MCLK применялись как выход MCO самого МК, так и отдельный кварцевый генератор на 12.288 МГц. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
digger2024 0 7 февраля Опубликовано 7 февраля · Жалоба Удалось добиться вывода тактового сигнала на на BCLK и WCLK, как от ADC_CLK, так и DAC_CLK, добавлением такого кода в инициализацию: //Sets AI = I2S, Data Word length = 20bit, BCLK is input, WCLK is input, DOUT will be high impedance after data has been transferred //AIC3204_I2C_WriteRegister(handle, AI_SETTING_R6, AI_SETTING_R6_Config); /* BCLK is output from the device*/ AIC3204_I2C_WriteRegister(handle, 0x1b, 0x0c); /* BDIV_CLKIN = DAC_CLK*/ AIC3204_I2C_WriteRegister(handle, 0x1d, 0x00); /* BCLK N divider = 1 */ AIC3204_I2C_WriteRegister(handle, 0x1e, 0x81); Однако основная проблема осталась нерешенной, так как мне так и настроить Digital Looopback в том виде, в котором я его понимаю, т. е. настроить выход АЦП напрямую к ЦАП. Как я уже ранее писал, через IN1R/L и Mixer все получается нормально. В таком случае, мне не совсем понятно назначение регистра: В данном случае речь идет о бите D4, который по идее должен соединить выход АЦП с входом ЦАП, чего в действительности не происходит. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
digger2024 0 20 февраля Опубликовано 20 февраля · Жалоба По итогу многочисленных попыток мне так и не удалось связать АЦП и ЦАП кодека изнутри, установка соответствующих битов в регистре P0_R29 ничего не дает, пришлось организовать тракт через MICPGA, MIXER AMPLIFIER, HP, т.е. по сути исключительно аналоговым путем, без предобразования АЦП -> ЦАП, и соответственно, без возможности применения встроенных цифровых фильтров. Сам ЦАП работает - удалось настроить на выход функцию BEEP. Вот рабочая конфигурация wait(1); /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, 0, 0); /* Software reset AIC3204 */ AIC3204_I2C_WriteRegister(handle, 1, 1); wait(1); /***************************************************** * PROGRAM CLOCK SETTINGS * Set DAC configuration * Set ADC configuration *****************************************************/ /*Set ADC configuration */ /* Set up the NADC divider with value */ AIC3204_I2C_WriteRegister(handle, 0x12, 0x81); /* Set up the MADC divider with value */ AIC3204_I2C_WriteRegister(handle, 0x13,0x82); /* Set up the ADCOSR with value */ AIC3204_I2C_WriteRegister(handle, 0x14, 0x40); //Set DAC configuration /* Set up the NDAC divider with value */ AIC3204_I2C_WriteRegister(handle, 0x0B, 0x81); //Set up the MDAC divider with value AIC3204_I2C_WriteRegister(handle, 0x0c, 0x82); /* Set up the DACOSR with value */ AIC3204_I2C_WriteRegister(handle, DAC_OSR_1, DAC_OSR_DIV>>8); AIC3204_I2C_WriteRegister(handle, DAC_OSR_2, 0x40); /* Select the ADC Mode */ AIC3204_I2C_WriteRegister(handle, 0x3d, 7); /*Select the DAC Mode*/ AIC3204_I2C_WriteRegister(handle, 0x3c, 25); //Sets AI = I2S, Data Word length = 20bit, BCLK is output, WCLK is output */ /* BCLK & WCLK is output from the device*/ AIC3204_I2C_WriteRegister(handle, 0x1b, 0x0c); /* BDIV_CLKIN = ADC_MOD_CLK */ AIC3204_I2C_WriteRegister(handle, 0x1d, 0x03); /* BCLK N divider powered up & BCLK N divider = 1 */ AIC3204_I2C_WriteRegister(handle, 0x1e, 0x81); /************************************************ * * PROGRAM 1st order IRR Filter Coefficients * * Sample Rate = 15600Hz * Filter 1 Low Pass 1st Order Butterworth, 4000 Hz Fc 0,0 dB " * * N0 = 0x4149FD N1 = 0x4149FD D1 = 0xFD6C04 * ************************************************/ /* Select Page 8 */ AIC3204_I2C_WriteRegister(handle, 0, 8); /* Left Channel N0 Reg - 24, 25 , 26*/ AIC3204_I2C_WriteRegister(handle, 0x18, 0x41); AIC3204_I2C_WriteRegister(handle, 0x19, 0x49); AIC3204_I2C_WriteRegister(handle, 0x1A, 0xFD); /* N1 Reg - 28, 29 , 30*/ AIC3204_I2C_WriteRegister(handle, 0x1C, 0x41); AIC3204_I2C_WriteRegister(handle, 0x1D, 0x49); AIC3204_I2C_WriteRegister(handle, 0x1E, 0xFD); /*D1 Reg - 32, 33, 34*/ AIC3204_I2C_WriteRegister(handle, 0x20, 0xFD); AIC3204_I2C_WriteRegister(handle, 0x21, 0x6C); AIC3204_I2C_WriteRegister(handle, 0x22, 0x04); /* Select Page 9*/ AIC3204_I2C_WriteRegister(handle, 0, 9); /* Right Channel N0 Reg - 24, 25 , 26*/ AIC3204_I2C_WriteRegister(handle, 0x20, 0x41); AIC3204_I2C_WriteRegister(handle, 0x21, 0x49); AIC3204_I2C_WriteRegister(handle, 0x22, 0xFD); /*N1 Reg - 28, 29 , 30*/ AIC3204_I2C_WriteRegister(handle, 0x24, 0x41); AIC3204_I2C_WriteRegister(handle, 0x25, 0x49); AIC3204_I2C_WriteRegister(handle, 0x26, 0xFD); /* D1 Reg - 32, 33, 34*/ AIC3204_I2C_WriteRegister(handle, 0x28, 0xFD); AIC3204_I2C_WriteRegister(handle, 0x29, 0x6C); AIC3204_I2C_WriteRegister(handle, 0x2A, 0x04); /************************************************ * * PROGRAM AGC BLOCKS * ************************************************/ /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, 0, 0); /* Left/Right Channel AGC Enabled & Left/Right Channel AGC Target Level = -12.0dBFS & Left/Right Channel AGC Gain Hysteresis is ±1.5dB */ AIC3204_I2C_WriteRegister(handle, 0x56, 0xD3); AIC3204_I2C_WriteRegister(handle, 0x5E, 0xD3); /* Left/Right Channel AGC Hysteresis 2dB & Left/Right Channel AGC noise Gate Threshold -90dB*/ AIC3204_I2C_WriteRegister(handle,0x57, 0xBE); AIC3204_I2C_WriteRegister(handle, 0x5F, 0xBE); /* Left Channel AGC Maximum Gain = 41.0dB*/ AIC3204_I2C_WriteRegister(handle,0x58, 0x52); AIC3204_I2C_WriteRegister(handle,0x60, 0x52); /* Left/Right Channel AGC Attack Time = 5*32 ADC Word Clocks & Left/Right Channel AGC Attack Time Scale Factor = 1 */ AIC3204_I2C_WriteRegister(handle,0x59, 0x08); AIC3204_I2C_WriteRegister(handle,0x61, 0x08); /* Left/Right Channel AGC Decay Time = 17*512 ADC Word Clocks*/ AIC3204_I2C_WriteRegister(handle,0x5A, 0x88); AIC3204_I2C_WriteRegister(handle,0x62, 0x88); /* Left/Right Channel AGC Noise Debounce Time =0 ADC Word Clock*/ AIC3204_I2C_WriteRegister(handle,0x5B, 0x0C); AIC3204_I2C_WriteRegister(handle,0x63, 0x0C); /* Left/Right Channel AGC Signal Debounce Time = 8 ADC Word Clocks*/ AIC3204_I2C_WriteRegister(handle,0x5C, 0x03); AIC3204_I2C_WriteRegister(handle,0x64, 0x03); /************************************************ * * PROGRAM I/O PINS * ************************************************/ /* Select Page 0 */ /* AIC3204_I2C_WriteRegister(handle, 0, 0); DOUT bus keep disabled AIC3204_I2C_WriteRegister(handle, 0x35, 0x10); DIN is disabled AIC3204_I2C_WriteRegister(handle, 0x36, 0x00); MISO buffer disabled AIC3204_I2C_WriteRegister(handle, 0x37, 0x00); SCLK pin is disabled AIC3204_I2C_WriteRegister(handle, 0x38, 0x00);*/ /************************************************ * * PROGRAM ANALOG BLOCKS * ************************************************/ /* Select Page 1 */ AIC3204_I2C_WriteRegister(handle, 0, 1); /*Set ADC configuration continue ... */ /*Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO */ AIC3204_I2C_WriteRegister(handle, 0x01, 0x08); /* Enable Master Analog Power Control */ AIC3204_I2C_WriteRegister(handle, 0x02, 0x00); /* Select ADC Power Tune Mode*/ AIC3204_I2C_WriteRegister(handle, 0x3d, 0xFF); /* Set the DAC PTM mode to PTM_P1 */ AIC3204_I2C_WriteRegister(handle, 0x03, 0x08); AIC3204_I2C_WriteRegister(handle, 0x03, 0x08); /* Set MicPGA startup delay */ AIC3204_I2C_WriteRegister(handle, 0x47, 0x32); /* Set the REF charging time */ AIC3204_I2C_WriteRegister(handle, 0x7b, 0x01); /*Full Chip Common Mode is 0.75V*/ //AIC3204_I2C_WriteRegister(handle, 0x0A, 0x40); /*Set MICPGA configuration */ /* Route IN1L to LEFT_P with 10K input impedance*/ AIC3204_I2C_WriteRegister(handle, 0x34, 0x40); /* Route IN3R Mode to LEFT_M with impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, 0x36, 0x40); /* Route IN1R to RIGHT_P with input impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, 0x37, 0x40); /* Route Common Mode to RIGHT_M with impedance of 10K*/ AIC3204_I2C_WriteRegister(handle, 0x39, 0x40); /* Unmute Left MICPGA & set volume*/ AIC3204_I2C_WriteRegister(handle, 0x3b, 0x00); /* Unmute Right MICPGA & set volume*/ AIC3204_I2C_WriteRegister(handle, 0x3c, 0x00); /* MICBIAS Power up & voltage is generated from AVDD & MICBIAS is switch to power supply */ AIC3204_I2C_WriteRegister(handle, 0x33, 0x70); /********************************************************************* * * POWER UP ADC * ********************************************************************/ /* Select Page 0 */ AIC3204_I2C_WriteRegister(handle, 0, 0); /* Power up Left and Right ADC Channels & ADC Volume Control Soft-Stepping disabled */ AIC3204_I2C_WriteRegister(handle, 0x51, 0xC2); /* Unmute Left and Right ADC Digital Volume Control. */ AIC3204_I2C_WriteRegister(handle, 0x52, 0x00); /* Set Left and Right ADC Digital Volume Control. */ //AIC3204_I2C_WriteRegister(handle, 0x53, 0x14); //AIC3204_I2C_WriteRegister(handle, 0x54, 0x14); /******************************************************************* * * PLAYBACK SETUP * ******************************************************************/ /* Select Page 1*/ AIC3204_I2C_WriteRegister(handle, 0, 1); /* HP soft stepping settings for optimal pop performance at power up * Rpop used is 6k with N = 6 and soft step = 0*/ //AIC3204_I2C_WriteRegister(handle, 0x14, 0x25); /*Left Channel DAC routed to HPLRoute, Left Mixer to HPL*/ AIC3204_I2C_WriteRegister(handle, 0x0c, 0x0A); /* Right Channel DAC routed to HPR, Route Right Mixer to HPR*/ AIC3204_I2C_WriteRegister(handle, 0x0d, 0x0A); /* IN1L to HPL Volume Control = -72.0dB*/ AIC3204_I2C_WriteRegister(handle, 0x16, 0x74); /* IN1R to HPR Volume Control = - 72.0dB*/ AIC3204_I2C_WriteRegister(handle, 0x17, 0x74); /*Mixer to HPL Volume Control = -12.6dB*/ AIC3204_I2C_WriteRegister(handle, 0x18, 0x23); /* Mixer to HPR Volume Control = -12.6dB*/ AIC3204_I2C_WriteRegister(handle, 0x19, 0x23); /* Power up HPL and HPR drivers */ AIC3204_I2C_WriteRegister(handle, 0x09, 0x33); /* Output Common Mode for HPL and HPR is 1.25V */ AIC3204_I2C_WriteRegister(handle, 0x0A, 0x00); /* Unmute HPL driver*/ AIC3204_I2C_WriteRegister(handle, 0x10, 0x16); /* Unmute HPR driver*/ AIC3204_I2C_WriteRegister(handle, 0x11, 0x16); /*Wait for 2 sec for soft stepping to take effect*/ wait(100); /* Select Page 0*/ AIC3204_I2C_WriteRegister(handle, 0, 0); /* Mute RDAC & up LDAC */ AIC3204_I2C_WriteRegister(handle, 0x40, 0x0C); /* Set up RDAC & up LDAC Initial Volume*/ AIC3204_I2C_WriteRegister(handle, 0x41, 0x00); AIC3204_I2C_WriteRegister(handle, 0x42, 0x00); /*Power up the Left and Right DAC Channels with route the Left Audio digital data to Left Channel DAC and Right Audio digital data to Right Channel DAC*/ AIC3204_I2C_WriteRegister(handle, 0x3f, 0x16) Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
