[Maverick_ 15]

Всем привет

есть проект - компилируется...

когда запускю симуляцию, то появляется ошибка  

Starting static elaboration
ERROR: [VRFC 10-1378] slice direction differs from its index type range [D:/project/xilinx/hdl/correlation_demodulator/source_hdl/shift_srl_delay_bus.vhd:76]
ERROR: [VRFC 10-664] expression has 32 elements ; expected 16 [D:/project/xilinx/hdl/correlation_demodulator/source_hdl/shift_srl_delay_bus.vhd:76]
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

как испраивить не пойму...

в проекте используется package

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

	package mod_pkg is
	
    constant NUM_INSTANCES       : integer := 128;
	constant NUM_PIPELINE		 : integer := 32;
    constant PIPELINE_STAGES     : integer := 15;
    constant RESET_ACTIVE_LEVEL  : std_logic := '1';
   	
   	constant AWIDTH : integer := NUM_PIPELINE/2; --:= 16;
	constant BWIDTH : integer := NUM_PIPELINE/2; --:= 16;
    
		
	type arr_reg_const is array (0 to (NUM_INSTANCES-1)) of std_logic_vector(NUM_PIPELINE-1 downto 0);
	type arr_comlex_reg_re is array (0 to (NUM_INSTANCES-1)) of std_logic_vector(AWIDTH-1 downto 0); -- (AWIDTH-1 downto 0)
	type arr_comlex_reg_im is array (0 to (NUM_INSTANCES-1)) of std_logic_vector(BWIDTH-1 downto 0); -- (BWIDTH-1 downto 0)
	
	type arr_comlex_result_re is array (0 to (NUM_INSTANCES-1)) of std_logic_vector(AWIDTH+BWIDTH downto 0);
	type arr_comlex_result_im is array (0 to (NUM_INSTANCES-1)) of std_logic_vector(AWIDTH+BWIDTH downto 0);
					
 end modulator_pkg;

в топе компонент обявлен:

 component shift_srl_delay_bus is
   generic (
    NUM_INSTANCES       : integer := 128;
	NUM_PIPELINE		  : integer := 32;
    PIPELINE_STAGES     : integer := 15;
    RESET_ACTIVE_LEVEL  : std_logic := '1'
  );

	port (
		clk   : in std_logic;
		rst   : in std_logic;
		valid     : in std_logic;
		data_in  : in std_logic_vector(NUM_PIPELINE-1 downto 0);
		data_re_out 	: out arr_comlex_reg_re;
		data_im_out 	: out arr_comlex_reg_im
	);
 end component;

-----

  shift_srl_delay_bus_inst : shift_srl_delay_bus
  generic map (
   NUM_INSTANCES       => NUM_INSTANCES,
   NUM_PIPELINE		   => NUM_PIPELINE,
   PIPELINE_STAGES     => PIPELINE_STAGES,
   RESET_ACTIVE_LEVEL  => '1'
)
	port map(
		clk   			=> clk,
		rst   			=> rst,
		valid           => valid,
		data_in  		=> data_in,
		data_re_out		=> reg_data_re,
		data_im_out 	=> reg_data_im
	);

само описание компонента

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library work;
use work.mod_pkg.all;

entity shift_srl_delay_bus is
  generic (
    NUM_INSTANCES       : integer := 128;
	NUM_PIPELINE		  : integer := 32;
    PIPELINE_STAGES     : integer := 15;
    RESET_ACTIVE_LEVEL  : std_logic := '1'
  );
  port (
    clk   : in std_logic;
    rst   : in std_logic;
    valid     : in std_logic;
    data_in  : in std_logic_vector(NUM_PIPELINE-1 downto 0);
    data_re_out 	: out arr_comlex_reg_re;
	data_im_out 	: out arr_comlex_reg_im
  );
end entity shift_srl_delay_bus;

architecture behavioral of shift_srl_delay_bus is

type t_const is array (0 to (NUM_INSTANCES-1)) of std_logic_vector(NUM_PIPELINE-1 downto 0);
signal reg_data_in  : t_const;
signal reg_data_out : t_const;

--signal reg_data_re : std_logic_vector(AWIDTH-1 downto 0);
--signal reg_data_im : std_logic_vector(BWIDTH-1 downto 0);

begin

  gen_pipeline_bus_inst : for i in 0 to NUM_INSTANCES-1 generate
    
  pipeline_bus_inst : entity work.pipeline_delay_bus
  generic map(
    NUM_INSTANCES       => NUM_PIPELINE,
    PIPELINE_STAGES     => PIPELINE_STAGES,--3
    RESET_ACTIVE_LEVEL  => '1'
  )
  port map(
    Clock   => clk,
    Reset   => rst,
    valid    => valid,
    Sig_in  => reg_data_in(i),
    Sig_out => reg_data_out(i),
    ready => open
  );
  end generate gen_pipeline_bus_inst;
  
 process(all)
 begin
 if rst = '1' then
        reg_data_in    <= (others => (others => '0'));
        data_re_out <= (others =>(others => '0'));
        data_im_out <= (others =>(others => '0'));
 elsif rising_edge(clk) then
 
      for i in reg_data_in'high downto reg_data_in'low + 1 loop
      --for i in 0 to (NUM_INSTANCES-1) loop
        reg_data_in(i) <= reg_data_out(i - 1);
      end loop;
 
      reg_data_in(reg_data_in'low) <= data_in;
      --data_out <= reg_data_out(reg_data_out'high);
 
  end if;
  
      for i in reg_data_in'high downto reg_data_in'low + 1 loop
      --for i in 0 to (NUM_INSTANCES-1) loop
            data_re_out(i) <= reg_data_in((NUM_PIPELINE/2)-1 downto 0)(i);				--!!!!!!!!
            data_im_out(i) <= reg_data_in(NUM_PIPELINE-1 downto NUM_PIPELINE/2)(i);		--!!!!!!!!
            
      end loop;
  
  end process;
  
end architecture behavioral;

ошибка в строке где в коментариях много !!!!

подскажите пожалуйста как подправить

[xvr 12]

data_re_out(i) <= reg_data_in(i)((NUM_PIPELINE/2)-1 downto 0);

?

[Maverick_ 15]

33 minutes ago, xvr said:

data_re_out(i) <= reg_data_in(i)((NUM_PIPELINE/2)-1 downto 0);

?

Огромное спасибо, помогло.... прямо в цель))))