[gosha-z 2]

3 hours ago, vladimirD said:

Я спрашивал на их форуме, ответил их модератор. Я как все проверю, выложу сюда детали с комментариями

Меня больше всего интересуют разделы IPI Mailboxes - остальные вроде понятны, если внимательно читать документацию.

[vladimirD 0]

Было две основных проблемы:

1) Пересекались регионы памяти в system-user.dtsi

2) Нужно было добавить разделы в system-user.dtsi для второго ядра R5_1

3) Нужно подправить Linux и Standalone applications для второго ядра R5_1 как описано в UG1186

Мой обновленный system-user.dtsi

 

/include/ "system-conf.dtsi"
/ {

	fclk0 {
		status = "okay";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		rproc_0_reserved: rproc@3ed000000 {
		no-map;
		reg = <0x0 0x3ed00000 0x0 0x2090000>;
		};
	};

	amba {
	/* Shared memory */
		shm0: shm@0 {
		compatible = "shm_uio";
		reg = <0x0 0x3ed80000 0x0 0x1000000>;
	};
	/* Shared memory */
		shm1: shm@1 {
		compatible = "shm_uio";
		reg = <0x0 0x3fd90000 0x0 0x1000000>;
	};	
	/* IPI device */
		ipi_amp0: ipi@ff340000 {
		compatible = "ipi_uio";
		reg = <0x0 0xff340000 0x0 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <0 29 4>;
		};
	/* IPI device */
		ipi_amp1: ipi@ff350000 {
		compatible = "ipi_uio";
		reg = <0x0 0xff350000 0x0 0x1000>;
		interrupt-parent = <&gic>;
		interrupts = <0 30 4>;
		};		

	/* firmware memory nodes */
		r5_0_tcm_a: tcm@ffe00000 {
			compatible = "mmio-sram";
			reg = <0x0 0xFFE00000 0x0 0x10000>;
			pd-handle = <&pd_tcm_0_a>;
		};
		r5_0_tcm_b: tcm@ffe20000 {
			compatible = "mmio-sram";
			reg = <0x0 0xFFE20000 0x0 0x10000>;
			pd-handle = <&pd_tcm_0_b>;
		};
		r5_1_tcm_a: tcm@ffe90000 {
			compatible = "mmio-sram";
			reg = <0 0xFFE90000 0x0 0x10000>;
			pd-handle = <&pd_tcm_1_a>;
		};
		r5_1_tcm_b: tcm@ffe92000 {
			compatible = "mmio-sram";
			reg = <0 0xFFEB0000 0x0 0x10000>;
			pd-handle = <&pd_tcm_1_b>;
		};		
		elf_ddr_0: ddr@3ed00000 {
			compatible = "mmio-sram";
			reg = <0x0 0x3ed00000 0x0 0x40000>;
		};
		elf_ddr_1: ddr@3ed40000 {
			compatible = "mmio-sram";
			reg = <0 0x3ed40000 0x0 0x40000>;
		};		
		test_r5_0: zynqmp_r5_rproc@0 {
			compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
			reg = <0x0 0xff9a0100 0 0x100>, <0x0 0xff340000 0 0x100>, <0x0 0xff9a0000 0 0x100>;
			reg-names = "rpu_base", "ipi", "rpu_glbl_base";
			dma-ranges;
			core_conf = "split0";
			srams = <&r5_0_tcm_a &r5_0_tcm_b &elf_ddr_0>;
			pd-handle = <&pd_r5_0>;
			interrupt-parent = <&gic>;
			interrupts = <0 29 4>;
		};
		test_r5_1: zynqmp_r5_rproc@1 {
			compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
			reg =<0x0 0xff9a0200 0 0x100>, <0x0 0xff340000 0 0x100>, <0x0 0xff9a0000 0 0x100>;
			reg-names = "rpu_base", "ipi", "rpu_glbl_base";
			dma-ranges;
			core_conf = "split1";
			srams = <&r5_1_tcm_a &r5_1_tcm_b &elf_ddr_1>;
			pd-handle = <&pd_r5_1>;
			interrupt-parent = <&gic>;
			interrupts = <0 29 4>;			
		} ;
	};

	power-domains {
		pd_r5_0: pd_r5_0 {
			#power-domain-cells = <0x0>;
			pd-id = <0x7>;
		};
		pd_r5_1: pd_r5_1 {
			#power-domain-cells = <0x0>;
			pd-id = <0x8>;
		};		
		pd_tcm_0_a: pd_tcm_0_a {
			#power-domain-cells = <0x0>;
			pd-id = <0xf>;
		};
		pd_tcm_0_b: pd_tcm_0_b {
			#power-domain-cells = <0x0>;
			pd-id = <0x10>;
		};
		pd_tcm_1_a: pd_tcm_1_a {
			#power-domain-cells = <0x0>;
			pd-id = <0x11>;
		};
		pd_tcm_1_b: pd_tcm_1_b {
			#power-domain-cells = <0x0>;
			pd-id = <0x12>;
		};		
	};

};

&ttc0 {
	compatible = "ttc0";
	status = "okay";
};
&ttc1 {
	compatible = "ttc1";
	status = "okay";
};

/* Default ethernet on the AVNET SoM */
&gem3 {
	status = "okay";
	local-mac-address = [00 0a 35 00 02 90];
	phy-mode = "rgmii-id";
	phy-handle = <&phy0>;
	phy0: phy@9 {
		reg = <0x9>;
		ti,rx-internal-delay = <0x5>;
		ti,tx-internal-delay = <0x5>;
		ti,fifo-depth = <0x1>;
	};
};

&i2c0 {
	status = "okay";
	clock-frequency = <400000>;

	oled@3c {
		status = "okay";
		compatible = "newhaven,oled-nhd-0420cw";
		reg = <0x3c>;
		enable-vdd-five-volt-reg = <0x00>;  /* 0x01 = enable, 0x00 disable and use 2.8v */
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	i2cswitch@70 { /* U7 on UZ3EG SOM */
		compatible = "nxp,pca9542";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		i2c@0 { /* i2c mw 70 0 1 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			/* IIC_EEPROM */
			eeprom@51 { /* U5 on UZ3EG IOCC and U7 on the UZ7EV EVCC*/
				compatible = "at,24c08";
				reg = <0x51>;
			};
		};
		i2c@1 { /* i2c mw 70 0 1 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
			/* Temp Sensor - LM75 compatible */
			lm75@48 {
				status = "okay";
				compatible = "maxim,mcp980x";
				reg = <0x48>;
			};
		};
	};
};

&qspi {
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";
	is-dual = <1>; /* Set for dual-parallel QSPI config */
	num-cs = <2>;
	xlnx,fb-clk = <0x1>;
	flash0: flash@0 {
        /* The Flash described below doesn't match our board ("micron,n25qu256a"), but is needed */
        /* so the Flash MTD partitions are correctly identified in /proc/mtd */
		compatible = "micron,m25p80"; /* 32MB */
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
		spi-max-frequency = <108000000>; /* Set to 108000000 Based on DC1 spec */
	};
};

/* SD0 eMMC, 8-bit wide data bus */
&sdhci0 {
	status = "okay";
	bus-width = <8>;
	max-frequency = <50000000>;
};

/* ULPI SMSC USB3320 */
&usb0 {
	status = "okay";
};

&dwc3_0 {
	status = "okay";
	dr_mode = "host";
	phy-names = "usb3-phy";
};

 

system-user.zip

[gosha-z 2]

Интересно еще увидеть system-conf.dtsi и выдачу dmesg после загрузки. Заранее спасибо.