[___sergey___ 0]

If the code is legal VHDL:

Answer whether the behaviour of the signal z has the same behaviour as in the main architecture of sumit.

entity sumit is
port (
     a, b, clk : in std_logic;
     z : out std_logic
);
end sumit;

architecture main of sumit is
signal m : std_logic;
begin
     process ( clk )
     begin
         if rising_edge( clk ) then
                m <= a or b; 
         end if;
     end process;

     process ( clk )
     begin
         if rising_edge( clk ) then 
             z <= not m;
         end if;
     end process;
end main;

architecture  main_1 of sumit is
signal m : std_logic;
begin
    process ( clk )
    begin
        if rising_edge( clk ) then
            m <= a or b;
            z <= not m;
        end if;
    end process;
end  main_1;

architecture  main_ 2 of sumit is
signal m, p : std_logic;
begin
    process ( clk )
    begin
        if rising_edge( clk ) then
            m <= a or b;
        end if;
    end process;

    process ( clk )
    begin
        if rising_edge( clk )
            then z <= p;
        end if;
     end process;

    p <= not m;

end  main_ 2;

[bookd 0]

main and main_2 have the same behaviour

main_1 gets result on the next edge.

Изменено 17 ноября, 2012 пользователем bookd

[winipuh 0]

architecture main

 

architecture main_1

 

architecture main_2

 

Tthey are all the same... IMHO :)

[maxfox2k 0]

во всех трёх вариантах будет один результат