Сейчас реализовано вот так вот.
(* bram_map="yes" *)
module RASP8192X16M16(DOUT,AD,CEN,CLK,DIN,OE,WE);
output [15:0]DOUT; // output data (read)
input CLK; // clock
input CEN; // chip enable (active low)
input WE; // write enable (active low)
input [12:0] AD; // addres of memory
input [15:0] DIN; // input data (write)
input OE;
// Only for TEST
reg [15:0] DOUT;
reg [15:0] mem [0:8191]; //4095
always @(posedge CLK)
begin
if (CEN == 1'b0) // clock enable
if (WE == 1'b1) mem [AD] <= DIN; // write operation
else
if (OE == 1'b1) DOUT <= mem [AD]; // read operation
end
endmodule
Но синтезатор пишет
INFO:Xst:2664 - HDL ADVISOR - Unit <RASP8192X16M16> : The RAM <Mram_mem> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
Хотя описание полностью синхронное, по одному CLK.
