Контроллер - stm32mp157. Прерывание UEV нужно, на нем строится логика отслеживания пропадания сигнала.
CNT сбрасывается аппаратно по входному сигналу, таймер в slave mode. Выходит, причина генерации UEV - это сброс таймера, но не по переполнению счетчика?
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event.
Таймер сконфигурирован таким образом
Particular case
To facilitate the input capture measurement, the timer counter is reset after each rising edge detected on the timer input channel by:
• Selecting TIxFPx as the input trigger by setting the TS bits in the SMCR register
• Selecting the reset mode as the slave mode by configuring the SMS bits in the SMCR
register.
Using this configuration, when an edge is detected, the counter is reset and the period of the external signal is automatically given by the value on the CCRx register. This method is used only with channel 1 or channel 2.
TIMx_SMCR
SMS[3:0]: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
...
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
...
TIMx_CR2
MMS[2:0]: Master mode selection
These bits allow selected information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
То есть цепочка такая - по входному сигналу сбрасывается счетчик, выставляется бит UG bit from the TIMx_EGR, генерится UEV , возникает прерывание?
Хотя про UG написано, что он устанавливается программно
TIMx_EGR
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an update of the registers. The prescaler internal
counter is also cleared (the prescaler ratio is not affected). The counter is cleared if the
center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value
(TIMx_ARR) if DIR=1 (downcounting).
Ответ на вопрос лежал на поверхности, благодарю.
TIMx_SR
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
At overflow or underflow (for TIM2 to TIM4) and if UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and
UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.
Теперь вопрос, как тогда отслеживать пропадание сигнала в этом режиме таймера.
PS Уведомления об ответах не приходили, странно...
