[k2i 0]

Возможно ли смешанное моделирование SystemC - VHDL ?

Например в VHDL установить компонент, написанный на SystemC

или для VHDL-компонента написать тестбенч на SystemC.

[YuryL 0]

возможно

например в modelsim6.0

[k2i 0]

Вот ещё:

 

Riviera 2004.12 has extended the support for SystemC by allowing designers to instantiate VHDL and Verilog modules in SystemC code, providing complete coverage of all possible combinations of HDL and SystemC modules in the design hierarchy. The ability to instantiate HDL in SystemC, without the PLI/VHPI overhead or cumbersome wrappers, is essential to high-level testbench development in HDL. The latest release also includes the MinGW package. MinGW is an open source package that includes a GCC compiler and a GDB debugger, which allow designers to perform co-simulation with SystemC and HDL.

 

h**p://www.aldec.com/Press/Releases/?ID=276&year=2004