Нужно получить сигнал стринг, вычленить из него символ и отправить в порт.
В таком варианте ISE выдает ошибку, но не говорит в какой строке.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity displey is
port (
clk : in STD_LOGIC;
RW: out STD_LOGIC;
RS: out STD_LOGIC;
E : out STD_LOGIC;
DB: inout STD_LOGIC_VECTOR(3 downto 0)
);
end displey;
architecture Behavioral of displey is
---------------------перевод символов в ASCII 8 значный код-----------------
function char_to_std_logic_vector(simbol:character) return STD_LOGIC_VECTOR;
function char_to_std_logic_vector(simbol:character) return STD_LOGIC_VECTOR is
variable vector: STD_LOGIC_VECTOR(7 downto 0):= "00000000";
begin
case (simbol) is
------words
when 'A' => vector:="01000001";
when 'B' => vector:="01000010";
--------special simbol
when 'п' => vector:="11110011";
when 'т' => vector:="11100110";
when 'ф' => vector:="00000001";
--------sign
when '|' => vector:="01111100";
when ' ' => vector:="00100000";
when '!' => vector:="00100001";
when ',' => vector:="00101100";
when '-' => vector:="00101101";
when '.' => vector:="00101110";
when '/' => vector:="00101111";
when ':' => vector:="00111010";
when others => null;
end case;
return vector;
end function char_to_std_logic_vector;
signal first_str: STRING (1 to 26):= "A:0000B:0000|п:0000т:0000|";
begin
process (clk)
variable simbol_code: STD_LOGIC_VECTOR (7 downto 0);
begin
simbol_code:= char_to_std_logic_vector(simbol=>first_str(current_simbol));
end process;
end Behavioral;