[ecos-rtos.in.ua 0]

Подключил к FPGA самодельную плату с TFT экраном. Портировал на этот экран модуль развертки от Jonathon W. Donaldson с opencores.org. Экран работает, при подключении "1" на входы RGB меняется цвет экрана.

Решил отобразить картинку, подключил в проекте image_gen_bram, тут случился затык.

 

http://paste.ubuntu.com/637762/

Кусок кода:

...
ARCHITECTURE image_gen_bram_arch OF image_gen_bram IS
   
   constant C_NUM_LCD_PIXELS : positive := 480;  -- number of drawable pixels per line in the LCD
   
   --Connecting signal wires between components
   signal SINIT_wire : std_logic := '0';
   signal ADDR_wire  : std_logic_vector(C_BRAM_ADDR_WIDTH-1 downto 0) := (others => '0');

begin

  image_RED_data : image_gen_bram_red
  port map (
    clka => CLK_LCD,
    addra => ADDR_wire,
    
    -- OUTPUTS --
    douta => R
  );
....

 

C_BRAM_ADDR_WIDTH : POSITIVE := 11; определено в модуле высшего уровня.

 

IP ядро Block Memory Generator дало такой template

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT image_gen_bram_red
  PORT (
    clka : IN STD_LOGIC;
    addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

 

Помогите решить проблему с

ERROR:Xst:2587 - Port <addra> of instance <image_RED_data> has different type in definition <image_gen_bram_red>.

 

Проект выложил здесь http://www.4shared.com/file/u1mt-2NL/TFT_FPGA_initial.html

[tegumay 4]

(выстрел прошел мимо)

 

positive сотрите или забейте константу и проверьте в чем дело.

[ecos-rtos.in.ua 0]

(выстрел прошел мимо)

 

positive сотрите или забейте константу и проверьте в чем дело.

Забил константу

signal ADDR_wire : std_logic_vector(11-1 downto 0) := (others => '0');

Ошибка:

ERROR:HDLParsers:837 - "E:/lin/TFT_FPGA_initial/image_gen_bram.vhd" Line 130. Width mismatch. Expected width 17, Actual width is 11 for dimension 1 of ADDR_wire.
ERROR:HDLParsers:837 - "E:/lin/TFT_FPGA_initial/image_gen_bram.vhd" Line 139. Width mismatch. Expected width 17, Actual width is 11 for dimension 1 of ADDR_wire.
ERROR:HDLParsers:837 - "E:/lin/TFT_FPGA_initial/image_gen_bram.vhd" Line 148. Width mismatch. Expected width 17, Actual width is 11 for dimension 1 of ADDR_wire.

Поставил 17, получил другую

signal ADDR_wire : std_logic_vector(17-1 downto 0) := (others => '0');

 

ERROR:NgdBuild:76 - File "ipcore_dir/image_gen_bram_red.ngc" cannot be merged
   into block "IMAGE/image_BLUE_data" (TYPE="image_gen_bram_red") because one or
   more pins on the block, including pin "addra<16>", were not found in the
   file.  Please make sure that all pins on the instantiated component match
   pins in the lower-level design block (irrespective of case).  If there are
   bussed pins on this block, make sure that the upper-level and lower-level
   netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File "ipcore_dir/image_gen_bram_red.ngc" cannot be merged
   into block "IMAGE/image_GREEN_data" (TYPE="image_gen_bram_red") because one
   or more pins on the block, including pin "addra<16>", were not found in the
   file.  Please make sure that all pins on the instantiated component match
   pins in the lower-level design block (irrespective of case).  If there are
   bussed pins on this block, make sure that the upper-level and lower-level
   netlists use the same bus-naming convention.
ERROR:NgdBuild:76 - File "ipcore_dir/image_gen_bram_red.ngc" cannot be merged
   into block "IMAGE/image_RED_data" (TYPE="image_gen_bram_red") because one or
   more pins on the block, including pin "addra<16>", were not found in the
   file.  Please make sure that all pins on the instantiated component match
   pins in the lower-level design block (irrespective of case).  If there are
   bussed pins on this block, make sure that the upper-level and lower-level
   netlists use the same bus-naming convention.
ERROR:NgdBuild:604 - logical block 'IMAGE/image_BLUE_data' with type
   'image_gen_bram_red' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'image_gen_bram_red' is not supported in target 'spartan3e'.
ERROR:NgdBuild:604 - logical block 'IMAGE/image_GREEN_data' with type
   'image_gen_bram_red' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'image_gen_bram_red' is not supported in target 'spartan3e'.
ERROR:NgdBuild:604 - logical block 'IMAGE/image_RED_data' with type
   'image_gen_bram_red' could not be resolved. A pin name misspelling can cause
   this, a missing edif or ngc file, case mismatch between the block name and
   the edif or ngc file name, or the misspelling of a type name. Symbol
   'image_gen_bram_red' is not supported in target 'spartan3e'.

[BlackOps 0]

Забил константу

signal ADDR_wire : std_logic_vector(11-1 downto 0) := (others => '0');

это не константа.

 

 

constant ADDR_wire : std_logic_vector(10 downto 0) := (others => '0');