MaratZuev 0 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба Всем добра! Имеются следующие файлы: process.bat @echo off set quartus_project_name=d44_m call clear_quartus call quartus_sh_compile_current_project pause clear_quartus.bat Spoiler @echo off echo %~n0 started at %time% %date% with %quartus_project_name% :process_folders set folders2delete=incremental_db, db, output_files, simulation for %%l in (%folders2delete%) do call :check_and_delete_folder %%l goto process_files : check_and_delete_folder if exist %1\ ( rmdir /s /q %1 echo Folder %1 is deleted ) exit /b :process_files set files2delete=%quartus_project_name%_assignment_defaults.qdf, *.done, *.jdi, *.pin, *.pof, *.rpt, *.sld, *.smsg, *.summary, *.sv, *.svh for %%l in (%files2delete%) do call :check_and_delete_file %%l goto finish : check_and_delete_file if exist %1 ( del /q %1 echo File %1 is deleted ) exit /b :finish echo %~n0 finished at %time% %date% exit /b quartus_sh_compile_current_project.bat Spoiler @echo off echo %~n0 is started at %time% %date% set QuartusProjectExtension=qpf for %%f in (*.%QuartusProjectExtension%) do ( if %%~xf==.%QuartusProjectExtension% ( set Project=%%~nf echo Project = %%~nf ) ) set Quartus_sh=d:\altera\18.1\quartus\bin64\quartus_sh.exe %Quartus_sh% --flow compile %Project% exit /b d44_m.qpf QUARTUS_VERSION = "18.1" PROJECT_REVISION = "d44_m" d44_m.qsf set_global_assignment -name LAST_QUARTUS_VERSION "18.1.1 Lite Edition" set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id.tcl" set_global_assignment -name TOP_LEVEL_ENTITY build_id set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name SYSTEMVERILOG_FILE build_id.sv set_global_assignment -name FAMILY "MAX V" set_global_assignment -name DEVICE 5M2210ZF256C4 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "as input tri-stated" set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED" и, наконец, сам build_id.tcl Spoiler # Generates a Verilog module that contains a timestamp, physical address, and host name # from the current build. These values are available from the build_date, build_time # output ports of the build_id module in the build_id.sv # SystemVerilog source file. # # The format for each value is as follows: # Date - 32-bit hexadecimal number of the format ddmmyyyy # Time - 32-bit hexadecimal number of the format hhmmss # # Usage: # # To manually execute this script, source this file using the following Tcl commands: # source build_id.tcl # # To have this script automatically execute each time your project is built, use the # following command (see: http://www.altera.com/support/examples/tcl/auto_processing.html): # set_global_assignment -name PRE_FLOW_SCRIPT_FILE quartus_sh:build_id.tcl # # Comment out the last line to prevent the process from automatically executing when # the file is sourced. The process can then be executed with the following command: # generateBuildID_Verilog # # # For more information, see "build_identification.pdf" # # ================================================================================ proc GenerateBuildID_SystemVerilog {} { # Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html) set buildDate [ clock format [ clock seconds ] -format %d%m%Y ] set buildTime [ clock format [ clock seconds ] -format %H%M%S ] # Create a SystemVerilog header file for output set build_id_header "build_id.svh" if ![file exists build_id_header] { file delete build_id_header } set outputFile [open $build_id_header "w"] puts $outputFile "// File name : build_id.svh" puts $outputFile "// Description : header file for build_id.sv and build_id_tb.sv" puts $outputFile "" puts $outputFile "`ifndef _build_id_svh_" puts $outputFile "`define _build_id_svh_" puts $outputFile "" puts $outputFile " `define BUILD_ID_REG_WDT 32" puts $outputFile " `define BUILD_ID_REG_RNG \[`BUILD_ID_REG_WDT-1:0\]" puts $outputFile "" puts $outputFile "`endif" close $outputFile # Create a SystemVerilog file for output set build_id_sv "build_id.sv" if ![file exists build_id_sv] { file delete build_id_sv } set outputFile [open $build_id_sv "w"] puts $outputFile "// File name : build_id.sv" puts $outputFile "// Description : Build ID SystemVerilog Module" puts $outputFile "" puts $outputFile "// Date : $buildDate" puts $outputFile "// Time : $buildTime" puts $outputFile "" puts $outputFile "`include \"build_id.svh\"" puts $outputFile "" puts $outputFile "module build_id (" puts $outputFile "" puts $outputFile " output logic `BUILD_ID_REG_RNG build_date," puts $outputFile " output logic `BUILD_ID_REG_RNG build_time" puts $outputFile "" puts $outputFile ");" puts $outputFile "" puts $outputFile " assign build_date = `BUILD_ID_REG_WDT'h$buildDate;" puts $outputFile " assign build_time = `BUILD_ID_REG_WDT'h$buildTime;" puts $outputFile "" puts $outputFile "endmodule : build_id" close $outputFile puts "Generated build identification SystemVerilog module: [pwd]/$outputFile" puts "Date: $buildDate" puts "Time: $buildTime" } # Load Quartus II Tcl Project package package require ::quartus::project # Add the next line to get the execute_flow command package require ::quartus::flow set project d44_m # Only open if not already open if [project_exists $project] { project_open $project } else { project_new $project } # Comment out this lines to prevent the process from automatically executing when the file is sourced: GenerateBuildID_SystemVerilog execute_flow -analysis_and_elaboration # Close project project_close При запуске process.bat получаем следующее: Spoiler clear_quartus started at 11:23:15,43 17.09.2021 with d44_m clear_quartus finished at 11:23:15,47 17.09.2021 quartus_sh_compile_current_project is started at 11:23:15,48 17.09.2021 Project = d44_m Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Copyright (C) 2019 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Fri Sep 17 11:23:16 2021 Info: Command: quartus_sh --flow compile d44_m Info: Quartus(args): compile d44_m Info: Project Name = D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/d44_m Info: Revision Name = d44_m Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Processing started: Fri Sep 17 11:23:18 2021 Info: Command: quartus_sh -t build_id.tcl compile d44_m d44_m Info: Quartus(args): compile d44_m d44_m Info: ******************************************************************* Info: Running Quartus Prime Analysis & Elaboration Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Processing started: Fri Sep 17 11:23:19 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off d44_m -c d44_m --analysis_and_elaboration Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file build_id.sv Info (12023): Found entity 1: build_id File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 9 Info (12127): Elaborating entity "build_id" for the top level hierarchy Info: Quartus Prime Analysis & Elaboration was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4673 megabytes Info: Processing ended: Fri Sep 17 11:23:45 2021 Info: Elapsed time: 00:00:26 Info: Total CPU time (on all processors): 00:00:36 Info (23030): Evaluation of Tcl script build_id.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4726 megabytes Info: Processing ended: Fri Sep 17 11:23:46 2021 Info: Elapsed time: 00:00:28 Info: Total CPU time (on all processors): 00:00:37 Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Processing started: Fri Sep 17 11:23:48 2021 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off d44_m -c d44_m Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (12021): Found 1 design units, including 1 entities, in source file build_id.sv Info (12023): Found entity 1: build_id File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 9 Info (12127): Elaborating entity "build_id" for the top level hierarchy Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "build_date[0]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[1]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[2]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[3]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[4]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[5]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[6]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[7]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[8]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[9]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[10]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[11]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[12]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[13]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[14]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[15]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[16]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[17]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[18]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[19]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[20]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[21]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[22]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[23]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[24]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[25]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[26]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[27]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[28]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[29]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[30]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_date[31]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 11 Warning (13410): Pin "build_time[0]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[1]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[2]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[3]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[4]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[5]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[6]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[7]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[8]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[9]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[10]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[11]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[12]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[13]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[14]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[15]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[16]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[17]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[18]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[19]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[20]" is stuck at VCC File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[21]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[22]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[23]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[24]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[25]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[26]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[27]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[28]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[29]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[30]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Warning (13410): Pin "build_time[31]" is stuck at GND File: D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/build_id.sv Line: 14 Info (21057): Implemented 64 device resources after synthesis - the final resource count might be different Info (21058): Implemented 0 input pins Info (21059): Implemented 64 output pins Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 65 warnings Info: Peak virtual memory: 4695 megabytes Info: Processing ended: Fri Sep 17 11:24:12 2021 Info: Elapsed time: 00:00:24 Info: Total CPU time (on all processors): 00:00:38 Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Processing started: Fri Sep 17 11:24:15 2021 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off d44_m -c d44_m Info: qfit2_default_script.tcl version: #1 Info: Project = d44_m Info: Revision = d44_m Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (119006): Selected device 5M2210ZF256C4 for design "d44_m" Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info (176445): Device 5M570ZF256C4 is compatible Info (176445): Device 5M1270ZF256C4 is compatible Critical Warning (169085): No exact pin location assignment(s) for 64 pins of 64 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report. Critical Warning (332012): Synopsys Design Constraints File file not found: 'd44_m.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332144): No user constrained base clocks found in the design Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Warning (332068): No clocks defined in design. Info (332128): Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info (332127): Assuming a default timing requirement Info (332159): No clocks to report Warning (332068): No clocks defined in design. Info (186079): Completed User Assigned Global Signals Promotion Operation Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement Info (176211): Number of I/O pins in group: 64 (unused VREF, 3.3V VCCIO, 0 input, 64 output, 0 bidirectional) Info (176212): I/O standards used: 3.3-V LVTTL. Info (176215): I/O bank details before I/O pin placement Info (176214): Statistics of I/O banks Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 49 pins available Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 51 pins available Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 53 pins available Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 50 pins available Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning Info (170195): Router estimated average interconnect usage is 0% of the available device resources Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X11_Y0 to location X21_Y14 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped Info (170200): Optimizations that may affect the design's timing were skipped Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 Info (11888): Total time spent on timing analysis during the Fitter is 0.02 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Info (144001): Generated suppressed messages file D:/Anatoly/Work/Firms/MIEA/Others/Sertification/FPGA/Verification/Projects/MUP/3/D44/Linting/MIEA/Modules/build_id/Quartus/Emasculated/d44_m.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 5 warnings Info: Peak virtual memory: 5038 megabytes Info: Processing ended: Fri Sep 17 11:24:18 2021 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:02 Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Processing started: Fri Sep 17 11:24:21 2021 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off d44_m -c d44_m Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4651 megabytes Info: Processing ended: Fri Sep 17 11:24:22 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info (293026): Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Processing started: Fri Sep 17 11:24:23 2021 Info: Command: quartus_sta d44_m -c d44_m Info: qsta_default_script.tcl version: #1 Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Critical Warning (332012): Synopsys Design Constraints File file not found: 'd44_m.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" Info (332096): The command derive_clocks did not find any clocks to derive. No clocks were created or changed. Warning (332068): No clocks defined in design. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info (332159): No clocks to report Info (332140): No fmax paths to report Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. Info (332140): No Setup paths to report Info (332140): No Hold paths to report Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332140): No Minimum Pulse Width paths to report Info (332001): The selected device family is not supported by the report_metastability command. Info (332101): Design is fully constrained for setup requirements Info (332101): Design is fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 2 warnings Info: Peak virtual memory: 4649 megabytes Info: Processing ended: Fri Sep 17 11:24:24 2021 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Info (293000): Quartus Prime Full Compilation was successful. 0 errors, 72 warnings Info (23030): Evaluation of Tcl script d:/altera/18.1/quartus/common/tcl/internal/qsh_flow.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 72 warnings Info: Peak virtual memory: 4704 megabytes Info: Processing ended: Fri Sep 17 11:24:25 2021 Info: Elapsed time: 00:01:09 Info: Total CPU time (on all processors): 00:00:01 Для продолжения нажмите любую клавишу . . . Правильно ли я понимаю, что, помимо компиляции tcl, quartus пытается провести полную сборку проекта? И, если да, то как мне заставить его ограничиться только компиляцией (созданием нужных мне модуля и хидера) и дальше не идти? Весь проект прилагаю. Emasculated.zip Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
andrew_b 14 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба tcl не надо компилировать. Это интерпретируемый язык. Чтобы только синтезтровать, надо вызывать quartus_map. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба 4 hours ago, andrew_b said: надо вызывать quartus_map. Вызываю так: quartus_map %QuartusProjectName% Получаю: Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
Nick_K 0 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба Я не сильно вникал в скрипт, да и с Ква не работал особо, но то что проект называется d44_m, а топ-левел файл build_id немного смущает. Да и при попытке билда почему-то указывается последний, хотя в самом первом скрипте 6 hours ago, MaratZuev said: set project d44_m Попробуйте посмотреть в этом направлении. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба 1 minute ago, Nick_K said: Попробуйте посмотреть в этом направлении. Прошу простить, что не оповестил, но я переписал все файлы проекта в одинообразном стиле и убрал упоминание проекта высшего уровня. Теперь есть build_id.qpf QUARTUS_VERSION = "18.1" PROJECT_REVISION = "build_id" build_id.qsf set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:build_id.tcl" set_global_assignment -name TOP_LEVEL_ENTITY build_id set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL set_global_assignment -name SYSTEMVERILOG_FILE build_id.sv process.bat @echo off set QuartusProjectExtension=qpf for %%f in (*.%QuartusProjectExtension%) do ( if %%~xf==.%QuartusProjectExtension% ( set QuartusProjectName=%%~nf echo QuartusProjectName = %%~nf ) ) call clear_quartus call quartus_map_current_project pause и, наконец, quartus_map_current_project.bat @echo off echo %~n0 started at %time% %date% with %QuartusProjectName% set quartus_map=c:\altera\13.1\SE\quartus\bin64\quartus_map.exe %quartus_map% %QuartusProjectName% echo %~n0 finished at %time% %date% exit /b остальное осталось тем же. Так что вопрос остаётся. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
andrew_b 14 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба 1 час назад, MaratZuev сказал: Получаю: Вставлять текст картинкой -- моветон. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба 1 hour ago, andrew_b said: Вставлять текст картинкой -- моветон. Моветон - это когда картинка не несёт никакой дополнительной информации. Напишете подсветку синтаксиса для того, что изображено на картинке - вопрос будет полностью правомерен. А так - критика ради критики. Пожалуйста: QuartusProjectName = build_id Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition Info: Copyright (C) 2019 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details, at Info: https://fpgasoftware.intel.com/eula. Info: Processing started: Fri Sep 17 21:42:18 2021 Info: Command: quartus_map build_id Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected Warning (12019): Can't analyze file -- file build_id.sv is missing Error (12007): Top-level design entity "build_id" is undefined Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 4675 megabytes Error: Processing ended: Fri Sep 17 21:42:41 2021 Error: Elapsed time: 00:00:23 Error: Total CPU time (on all processors): 00:00:01 Для продолжения нажмите любую клавишу . . . В скрепке скорректированный проект .... Всё на том же месте. build_id.zip Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
wolfman 0 17 сентября, 2021 Опубликовано 17 сентября, 2021 · Жалоба 2 часа назад, MaratZuev сказал: Warning (12019): Can't analyze file -- file build_id.sv is missing Error (12007): Top-level design entity "build_id" is undefined Вам же чёрным по английскому пишут. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 18 сентября, 2021 Опубликовано 18 сентября, 2021 · Жалоба 10 hours ago, wolfman said: Вам же чёрным по английскому пишут. Вот спасибо: а я-то английкого-то и не знаю! Куда уж нам, сиворылым! Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 19 сентября, 2021 Опубликовано 19 сентября, 2021 · Жалоба ActiveTCL спас отца русской демократии. Окончательный проект прилагаю. build_id_activetcl.zip Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
Nick_K 0 19 сентября, 2021 Опубликовано 19 сентября, 2021 · Жалоба 1 hour ago, MaratZuev said: ActiveTCL спас отца русской демократии. Окончательный проект прилагаю. build_id_activetcl.zip 1.99 kB · 1 download А чем же так полезен оказался ActiveTCL?.. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 19 сентября, 2021 Опубликовано 19 сентября, 2021 · Жалоба 1 hour ago, Nick_K said: А чем же так полезен оказался ActiveTCL?.. Он позволил исключить Quartus из цепочки, в которой последний был вообще не нужен и с которым прому(вырезано цензурой)дохался и сам ТС и те, кто "пытался ему помогать". В любом случае всем спасибо (без кавычек), ибо без вас всех я бы не пришёл к этому (хотя здесь, м.б. немного лукавлю). Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
MaratZuev 0 20 сентября, 2021 Опубликовано 20 сентября, 2021 · Жалоба Орешек знаний тверд, Но все же мы не привыкли отступать... ---------------------------- quartus_asm --tcl_eval source build_id.tcl build_id.zip Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
