dsl2640free
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Постов
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Зарегистрирован
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Посещение
Сообщения, опубликованные dsl2640free
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Скрытый текст123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119/*** Keil project for very basic and primitive CPU load monitor** Before you start, select your target, on the right of the "Load" button** @author Tilen Majerle* @email [email protected]* @website http://stm32f4-discovery.net* @ide Keil uVision 5* @conf PLL parameters are set in "Options for Target" -> "C/C++" -> "Defines"* @packs STM32F4xx Keil packs version 2.4.0 or greater required* @stdperiph STM32F4xx Standard peripheral drivers version 1.5.0 or greater required*//* Include core modules */#include "stm32f4xx.h"/* Include my libraries here */#include "defines.h"#include "tm_stm32f4_delay.h"#include "tm_stm32f4_disco.h"#include "tm_stm32f4_general.h"#include "tm_stm32f4_usart.h"#include "stdio.h"/* Go to sleep mode */void GoToSleepMode(void);int main(void) {__IO uint32_t i;/* Initialize system */SystemInit();/* Init DWT timer to count processor cycles */TM_GENERAL_DWTCounterEnable();/* Reset counter */TM_GENERAL_DWTCounterSetValue(0);/* Initialize delay */TM_DELAY_Init();/* Initialize leds on board */TM_DISCO_LedInit();/* Initialize button */TM_DISCO_ButtonInit();/* Init USART2, TX: PA2, RX: PA3, 921600 baud */TM_USART_Init(USART2, TM_USART_PinsPack_1, 921600);while (1) {/* If button is pressed, do some useless dummy counting *//* Otherwise, go sleep directly */if (TM_DISCO_ButtonPressed()) {/* Do some while looping */i = 0;while (i++ < 0x2FFF);}/* Toggle leds */TM_DISCO_LedToggle(LED_ALL);/* Go to sleep mode */GoToSleepMode();}}void GoToSleepMode(void) {uint32_t t;static uint32_t l = 0;static uint32_t WorkingTime = 0;static uint32_t SleepingTime = 0;static uint32_t LastTime = 0;/* Disable interrupts */__disable_irq();/* Add to working time */WorkingTime += DWT->CYCCNT - l;/* Save count cycle time */t = DWT->CYCCNT;/* Go to sleep mode *//* Wait for wake up interrupt, systick can do it too */__WFI();/* Increase number of sleeping time in CPU cycles */SleepingTime += DWT->CYCCNT - t;/* Save current time to get number of working CPU cycles */l = DWT->CYCCNT;/* Enable interrupts, process/execute an interrupt routine which wake up CPU */__enable_irq();/* Every 1000ms print CPU load via USART */if ((TM_DELAY_Time() - LastTime) >= 1000) {/* Save new time */LastTime = TM_DELAY_Time();/* Print to user */printf("W: %u; S: %u; L: %5.2f %%\n", WorkingTime, SleepingTime, ((float)WorkingTime / (float)(SleepingTime + WorkingTime) * 100));/* Reset time */SleepingTime = 0;WorkingTime = 0;}}/* Handle printf functionality */int fputc(int ch, FILE* fil) {/* Send character over USART */TM_USART_Putc(USART2, ch);/* Return character */return ch;}
управление потребляемой мощностью в сложных устройствах.
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Похожая система реализована в iPhone. Обмен между приложением и кабелем, а через него и телефоном, зашифрован. В кабеле есть микросхема с ключами. Apple запрещает кабели с левыми фишками.
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Спойлер
Ниже приведен пример более сложной процедуры, которая использует DSP особенности dsPIC33E.
Спойлер#include <dsp.h>;
#define FFT_BLOCK_LENGTH 1024 //Number of frequency points in the FFT
#define LOG2_BLOCK_LENGTH 10 //Number of "Butterfly" Stages in FFT processing should be related to FFT_BLOCK as in 2^9=512
#define AUDIO_FS 44100//Sampling frequency of audio signal captured by the mic
int16_t peakFrequencyBin;
uint16_t ix_MicADCbuff;
uint16_t peakFrequency;
extern const fractcomplex twiddleFactors[FFT_BLOCK_LENGTH/2]__attribute__ ((space(auto_psv), aligned (FFT_BLOCK_LENGTH*2)));
fractcomplex sigCmpx[FFT_BLOCK_LENGTH] __attribute__ ((section (".ydata, data, ymemory"), aligned (FFT_BLOCK_LENGTH * 2 *2)))={{0}};
void readMic(void)//Sample microphone input
{
ADC1_ChannelSelectSet(ADC1_AI_MIC);
ix_MicADCbuff=0;
for(ix_MicADCbuff=0;ix_MicADCbuff<FFT_BLOCK_LENGTH;ix_MicADCbuff++)
{
//Insert delay subroutine here
ADC1_SamplingStop();
while(!ADC1_IsConversionComplete()){}
sigCmpx[ix_MicADCbuff].real = ADC1_Channel0ConversionResultGet();
sigCmpx[ix_MicADCbuff].imag = 0;
}
}
void signalFreq(void)//Detect the dominant frequency of the audio picked by the microphone
{
readMic();
FFTComplexIP (LOG2_BLOCK_LENGTH, &sigCmpx[0], (fractcomplex *) __builtin_psvoffset(&twiddleFactors[0]), (int) __builtin_psvpage(&twiddleFactors[0]));// Perform FFT operation
BitReverseComplex (LOG2_BLOCK_LENGTH, &sigCmpx[0]);// Store output samples in bit-reversed order of their addresses
SquareMagnitudeCplx(FFT_BLOCK_LENGTH, &sigCmpx[0], &sigCmpx[0].real);//Compute the square magnitude of the complex FFT output array so we have a Real output vector
VectorMax(FFT_BLOCK_LENGTH/2, &sigCmpx[0].real, &peakFrequencyBin);//Find the frequency Bin ( = index into the SigCmpx[] array) that has the largest energy
peakFrequency = peakFrequencyBin*(AUDIO_FS/FFT_BLOCK_LENGTH); //Compute the frequency (in Hz) of the largest spectral component
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кусок кода, детектирующий гармоники в составе сигнала
Спойлерpublic ArrayList<SynthesizableSignal> detectHarmonics() { SignalCutter cutter = new SignalCutter(source, new Signal(source)); SynthesizableComplexExponent heterodinParameter = new SynthesizableComplexExponent(); heterodinParameter.setProperty("frequency", 0.0); Signal heterodin = new Signal(source.getLength()); Signal heterodinedSignal = new Signal(cutter.getCurrentSignal()); Spectrum spectrum = new Spectrum(heterodinedSignal); int harmonic; while ((harmonic = spectrum.detectStrongPeak(min)) != -1) { if (cutter.getCuttersCount() > 10) throw new RuntimeException("Unable to analyze signal! Try another parameters."); double heterodinSelected = 0.0; double signalToNoise = spectrum.getRealAmplitude(harmonic) / spectrum.getAverageAmplitudeIn(harmonic, windowSize); for (double heterodinFrequency = -0.5; heterodinFrequency < (0.5 + heterodinAccuracy); heterodinFrequency += heterodinAccuracy) { heterodinParameter.setProperty("frequency", heterodinFrequency); heterodinParameter.synthesizeIn(heterodin); heterodinedSignal.set(cutter.getCurrentSignal()).multiply(heterodin); spectrum.recalc(); double newSignalToNoise = spectrum.getRealAmplitude(harmonic) / spectrum.getAverageAmplitudeIn(harmonic, windowSize); if (newSignalToNoise > signalToNoise) { signalToNoise = newSignalToNoise; heterodinSelected = heterodinFrequency; } } SynthesizableCosine parameter = new SynthesizableCosine(); heterodinParameter.setProperty("frequency", heterodinSelected); heterodinParameter.synthesizeIn(heterodin); heterodinedSignal.set(cutter.getCurrentSignal()).multiply(heterodin); spectrum.recalc(); parameter.setProperty("amplitude", MathHelper.adaptiveRound(spectrum.getRealAmplitude(harmonic))); parameter.setProperty("frequency", harmonic - heterodinSelected); parameter.setProperty("phase", MathHelper.round(spectrum.getPhase(harmonic), 1)); cutter.addSignal(parameter); cutter.cutNext(); heterodinedSignal.set(cutter.getCurrentSignal()); spectrum.recalc(); } return cutter.getSignalsParameters(); } -
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Надо замкнуть оба "automatic ISP jumpers" p31 и p36
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можно вот так инициализировать
Spoiler#include <xc.h> #include "epwm2.h" /** Section: Macro Declarations */ #define PWM2_INITIALIZE_DUTY_VALUE 511 /** Section: EPWM Module APIs */ void EPWM2_Initialize (void) { // Set the PWM to the options selected in MPLAB® Code Configurator // CCP2M P2AP2Chi_P2BP2Dlo; P2M halfbridge; DC2B 48; CCP2CON = 0xBD; // PSS2BD P2BP2D_0; CCP2AS disabled; CCP2ASE operating; PSS2AC P2AP2C_0; ECCP2AS = 0x00; // P2RSEN automatic_restart; P2DC 0; PWM2CON = 0x80; // STR2D P2D_to_port; STR2C P2C_to_port; STR2B P2B_to_port; STR2A P2A_to_port; STR2SYNC start_at_begin; PSTR2CON = 0x00; // CCPR2L 127; CCPR2L = 0x7F; // CCPR2H 0x0; CCPR2H = 0x00; // Selecting Timer2 CCPTMRS0bits.C2TSEL = 0x0; } void EPWM2_LoadDutyValue(uint16_t dutyValue) { // Writing to 8 MSBs of pwm duty cycle in CCPRL register CCPR2L = ((dutyValue & 0x03FC)>>2); // Writing to 2 LSBs of pwm duty cycle in CCPCON register CCP2CON = (CCP2CON & 0xCF) | ((dutyValue & 0x0003)<<4); } -
On 3/10/2019 at 10:34 PM, Koluchiy said:
2. CY7С68013-128AC - 3 штуки
3. CY7С68013A-128AXC - 3 штуки
Т.е. оба варианта по 3 штуки, всего 6. 500 рублей за штуку.
po 200 руб.
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специально взял попробовал - авторазмещение работает.
просто исправил файл pcb.ini - указад путь к спекктре и к файлам accel2sp и sp2accel (причем Спекктра довольно старая 9.02, да и конвертеры тоже не новые - проверенные временем) - и, как говорится,- вуаля! - все работает и результат возвращается обратно в PCAD.
Другой вопрос, что в Спекктре авторазмещение, в отличие от автотрассировщика, используется мало в силу неудовлетворительных результатов. Вручную оказывается практически всегда лучше, да и операция не такая трудоемкая -
У меня так тоже было. помогла специальная инициализация: GPIO_InitTypeDef GPIO_InitStructure; USART_InitTypeDef USART_InitStructure; NVIC_InitTypeDef NVIC_InitStructure; RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); //UART4_TX PC.10 PC.11 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10 | GPIO_Pin_11; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; GPIO_Init(GPIOC, &GPIO_InitStructure); GPIO_PinAFConfig(GPIOC, GPIO_PinSource10, GPIO_AF_UART4); GPIO_PinAFConfig(GPIOC, GPIO_PinSource11, GPIO_AF_UART4); //Usart1 NVIC NVIC_InitStructure.NVIC_IRQChannel = UART4_IRQn; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=3 ; NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; NVIC_Init(&NVIC_InitStructure); USART_InitStructure.USART_BaudRate = Baud; USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_Parity = USART_Parity_No; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; USART_Init(UART4, &USART_InitStructure); USART_ITConfig(UART4, USART_IT_RXNE, ENABLE); USART_Cmd(UART4, ENABLE); -
Spoiler
#include <linux/ctype.h> #include <linux/module.h> #include <linux/moduleparam.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/firmware.h> #include <linux/list.h> #include <linux/pm.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/slab.h> #include <linux/vmalloc.h> #include <linux/workqueue.h> #include <linux/debugfs.h> #include <sound/core.h> #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> #include <sound/jack.h> #include <sound/initval.h> #include <sound/tlv.h> #include "wm_adsp.h" #define adsp_crit(_dsp, fmt, ...) \ dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) #define adsp_err(_dsp, fmt, ...) \ dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) #define adsp_warn(_dsp, fmt, ...) \ dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) #define adsp_info(_dsp, fmt, ...) \ dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) #define adsp_dbg(_dsp, fmt, ...) \ dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__) #define compr_err(_obj, fmt, ...) \ adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ ##__VA_ARGS__) #define compr_dbg(_obj, fmt, ...) \ adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \ ##__VA_ARGS__) #define ADSP1_CONTROL_1 0x00 #define ADSP1_CONTROL_2 0x02 #define ADSP1_CONTROL_3 0x03 #define ADSP1_CONTROL_4 0x04 #define ADSP1_CONTROL_5 0x06 #define ADSP1_CONTROL_6 0x07 #define ADSP1_CONTROL_7 0x08 #define ADSP1_CONTROL_8 0x09 #define ADSP1_CONTROL_9 0x0A #define ADSP1_CONTROL_10 0x0B #define ADSP1_CONTROL_11 0x0C #define ADSP1_CONTROL_12 0x0D #define ADSP1_CONTROL_13 0x0F #define ADSP1_CONTROL_14 0x10 #define ADSP1_CONTROL_15 0x11 #define ADSP1_CONTROL_16 0x12 #define ADSP1_CONTROL_17 0x13 #define ADSP1_CONTROL_18 0x14 #define ADSP1_CONTROL_19 0x16 #define ADSP1_CONTROL_20 0x17 #define ADSP1_CONTROL_21 0x18 #define ADSP1_CONTROL_22 0x1A #define ADSP1_CONTROL_23 0x1B #define ADSP1_CONTROL_24 0x1C #define ADSP1_CONTROL_25 0x1E #define ADSP1_CONTROL_26 0x20 #define ADSP1_CONTROL_27 0x21 #define ADSP1_CONTROL_28 0x22 #define ADSP1_CONTROL_29 0x23 #define ADSP1_CONTROL_30 0x24 #define ADSP1_CONTROL_31 0x26 /* * ADSP1 Control 19 */ #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */ /* * ADSP1 Control 30 */ #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */ #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */ #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */ #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */ #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ #define ADSP1_START 0x0001 /* DSP1_START */ #define ADSP1_START_MASK 0x0001 /* DSP1_START */ #define ADSP1_START_SHIFT 0 /* DSP1_START */ #define ADSP1_START_WIDTH 1 /* DSP1_START */ /* * ADSP1 Control 31 */ #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ #define ADSP2_CONTROL 0x0 #define ADSP2_CLOCKING 0x1 #define ADSP2V2_CLOCKING 0x2 #define ADSP2_STATUS1 0x4 #define ADSP2_WDMA_CONFIG_1 0x30 #define ADSP2_WDMA_CONFIG_2 0x31 #define ADSP2V2_WDMA_CONFIG_2 0x32 #define ADSP2_RDMA_CONFIG_1 0x34 #define ADSP2_SCRATCH0 0x40 #define ADSP2_SCRATCH1 0x41 #define ADSP2_SCRATCH2 0x42 #define ADSP2_SCRATCH3 0x43 #define ADSP2V2_SCRATCH0_1 0x40 #define ADSP2V2_SCRATCH2_3 0x42 /* * ADSP2 Control */ #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */ #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */ #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */ #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */ #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */ #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */ #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */ #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */ #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */ #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */ #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */ #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */ #define ADSP2_START 0x0001 /* DSP1_START */ #define ADSP2_START_MASK 0x0001 /* DSP1_START */ #define ADSP2_START_SHIFT 0 /* DSP1_START */ #define ADSP2_START_WIDTH 1 /* DSP1_START */ /* * ADSP2 clocking */ #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */ #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */ #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ /* * ADSP2V2 clocking */ #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */ #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */ #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */ #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */ #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */ #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */ /* * ADSP2 Status 1 */ #define ADSP2_RAM_RDY 0x0001 #define ADSP2_RAM_RDY_MASK 0x0001 #define ADSP2_RAM_RDY_SHIFT 0 #define ADSP2_RAM_RDY_WIDTH 1 /* * ADSP2 Lock support */ #define ADSP2_LOCK_CODE_0 0x5555 #define ADSP2_LOCK_CODE_1 0xAAAA #define ADSP2_WATCHDOG 0x0A #define ADSP2_BUS_ERR_ADDR 0x52 #define ADSP2_REGION_LOCK_STATUS 0x64 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E #define ADSP2_LOCK_REGION_CTRL 0x7A #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C #define ADSP2_REGION_LOCK_ERR_MASK 0x8000 #define ADSP2_SLAVE_ERR_MASK 0x4000 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002 #define ADSP2_CTRL_ERR_EINT 0x0001 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD #define ADSP2_LOCK_REGION_SHIFT 16 #define ADSP_MAX_STD_CTRL_SIZE 512 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF /* * Event control messages */ #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001 struct wm_adsp_buf { struct list_head list; void *buf; }; static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len, struct list_head *list) { struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL); if (buf == NULL) return NULL; buf->buf = vmalloc(len); if (!buf->buf) { kfree(buf); return NULL; } memcpy(buf->buf, src, len); if (list) list_add_tail(&buf->list, list); return buf; } static void wm_adsp_buf_free(struct list_head *list) { while (!list_empty(list)) { struct wm_adsp_buf *buf = list_first_entry(list, struct wm_adsp_buf, list); list_del(&buf->list); vfree(buf->buf); kfree(buf); } } #define WM_ADSP_FW_MBC_VSS 0 #define WM_ADSP_FW_HIFI 1 #define WM_ADSP_FW_TX 2 #define WM_ADSP_FW_TX_SPK 3 #define WM_ADSP_FW_RX 4 #define WM_ADSP_FW_RX_ANC 5 #define WM_ADSP_FW_CTRL 6 #define WM_ADSP_FW_ASR 7 #define WM_ADSP_FW_TRACE 8 #define WM_ADSP_FW_SPK_PROT 9 #define WM_ADSP_FW_MISC 10 #define WM_ADSP_NUM_FW 11 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = { [WM_ADSP_FW_MBC_VSS] = "MBC/VSS", [WM_ADSP_FW_HIFI] = "MasterHiFi", [WM_ADSP_FW_TX] = "Tx", [WM_ADSP_FW_TX_SPK] = "Tx Speaker", [WM_ADSP_FW_RX] = "Rx", [WM_ADSP_FW_RX_ANC] = "Rx ANC", [WM_ADSP_FW_CTRL] = "Voice Ctrl", [WM_ADSP_FW_ASR] = "ASR Assist", [WM_ADSP_FW_TRACE] = "Dbg Trace", [WM_ADSP_FW_SPK_PROT] = "Protection", [WM_ADSP_FW_MISC] = "Misc", }; struct wm_adsp_system_config_xm_hdr { __be32 sys_enable; __be32 fw_id; __be32 fw_rev; __be32 boot_status; __be32 watchdog; __be32 dma_buffer_size; __be32 rdma[6]; __be32 wdma[8]; __be32 build_job_name[3]; __be32 build_job_number; }; struct wm_adsp_alg_xm_struct { __be32 magic; __be32 smoothing; __be32 threshold; __be32 host_buf_ptr; __be32 start_seq; __be32 high_water_mark; __be32 low_water_mark; __be64 smoothed_power; }; struct wm_adsp_host_buf_coeff_v1 { __be32 host_buf_ptr; /* Host buffer pointer */ __be32 versions; /* Version numbers */ __be32 name[4]; /* The buffer name */ }; struct wm_adsp_buffer { __be32 buf1_base; /* Base addr of first buffer area */ __be32 buf1_size; /* Size of buf1 area in DSP words */ __be32 buf2_base; /* Base addr of 2nd buffer area */ __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */ __be32 buf3_base; /* Base addr of buf3 area */ __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */ __be32 high_water_mark; /* Point at which IRQ is asserted */ __be32 irq_count; /* bits 1-31 count IRQ assertions */ __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */ __be32 next_write_index; /* word index of next write */ __be32 next_read_index; /* word index of next read */ __be32 error; /* error if any */ __be32 oldest_block_index; /* word index of oldest surviving */ __be32 requested_rewind; /* how many blocks rewind was done */ __be32 reserved_space; /* internal */ __be32 min_free; /* min free space since stream start */ __be32 blocks_written[2]; /* total blocks written (64 bit) */ __be32 words_written[2]; /* total words written (64 bit) */ }; struct wm_adsp_compr; struct wm_adsp_compr_buf { struct list_head list; struct wm_adsp *dsp; struct wm_adsp_compr *compr; struct wm_adsp_buffer_region *regions; u32 host_buf_ptr; u32 error; u32 irq_count; int read_index; int avail; int host_buf_mem_type; char *name; }; struct wm_adsp_compr { struct list_head list; struct wm_adsp *dsp; struct wm_adsp_compr_buf *buf; struct snd_compr_stream *stream; struct snd_compressed_buffer size; u32 *raw_buf; unsigned int copied_total; unsigned int sample_rate; const char *name; }; #define WM_ADSP_DATA_WORD_SIZE 3 #define WM_ADSP_MIN_FRAGMENTS 1 #define WM_ADSP_MAX_FRAGMENTS 256 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE) #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE) #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7 #define HOST_BUFFER_FIELD(field) \ (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32)) #define ALG_XM_FIELD(field) \ (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32)) #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8 static int wm_adsp_buffer_init(struct wm_adsp *dsp); static int wm_adsp_buffer_free(struct wm_adsp *dsp); struct wm_adsp_buffer_region { unsigned int offset; unsigned int cumulative_size; unsigned int mem_type; unsigned int base_addr; }; struct wm_adsp_buffer_region_def { unsigned int mem_type; unsigned int base_offset; unsigned int size_offset; }; static const struct wm_adsp_buffer_region_def default_regions[] = { { .mem_type = WMFW_ADSP2_XM, .base_offset = HOST_BUFFER_FIELD(buf1_base), .size_offset = HOST_BUFFER_FIELD(buf1_size), }, { .mem_type = WMFW_ADSP2_XM, .base_offset = HOST_BUFFER_FIELD(buf2_base), .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size), }, { .mem_type = WMFW_ADSP2_YM, .base_offset = HOST_BUFFER_FIELD(buf3_base), .size_offset = HOST_BUFFER_FIELD(buf_total_size), }, }; struct wm_adsp_fw_caps { u32 id; struct snd_codec_desc desc; int num_regions; const struct wm_adsp_buffer_region_def *region_defs; }; static const struct wm_adsp_fw_caps ctrl_caps[] = { { .id = SND_AUDIOCODEC_BESPOKE, .desc = { .max_ch = 8, .sample_rates = { 16000 }, .num_sample_rates = 1, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, .num_regions = ARRAY_SIZE(default_regions), .region_defs = default_regions, }, }; static const struct wm_adsp_fw_caps trace_caps[] = { { .id = SND_AUDIOCODEC_BESPOKE, .desc = { .max_ch = 8, .sample_rates = { 4000, 8000, 11025, 12000, 16000, 22050, 24000, 32000, 44100, 48000, 64000, 88200, 96000, 176400, 192000 }, .num_sample_rates = 15, .formats = SNDRV_PCM_FMTBIT_S16_LE, }, .num_regions = ARRAY_SIZE(default_regions), .region_defs = default_regions, }, }; static const struct { const char *file; int compr_direction; int num_caps; const struct wm_adsp_fw_caps *caps; bool voice_trigger; } wm_adsp_fw[WM_ADSP_NUM_FW] = { [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" }, [WM_ADSP_FW_HIFI] = { .file = "hifi" }, [WM_ADSP_FW_TX] = { .file = "tx" }, [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" }, [WM_ADSP_FW_RX] = { .file = "rx" }, [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" }, [WM_ADSP_FW_CTRL] = { .file = "ctrl", .compr_direction = SND_COMPRESS_CAPTURE, .num_caps = ARRAY_SIZE(ctrl_caps), .caps = ctrl_caps, .voice_trigger = true, }, [WM_ADSP_FW_ASR] = { .file = "asr" }, [WM_ADSP_FW_TRACE] = { .file = "trace", .compr_direction = SND_COMPRESS_CAPTURE, .num_caps = ARRAY_SIZE(trace_caps), .caps = trace_caps, }, [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" }, [WM_ADSP_FW_MISC] = { .file = "misc" }, }; struct wm_coeff_ctl_ops { int (*xget)(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); int (*xput)(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); }; struct wm_coeff_ctl { const char *name; const char *fw_name; struct wm_adsp_alg_region alg_region; struct wm_coeff_ctl_ops ops; struct wm_adsp *dsp; unsigned int enabled:1; struct list_head list; void *cache; unsigned int offset; size_t len; unsigned int set:1; struct soc_bytes_ext bytes_ext; unsigned int flags; unsigned int type; }; static const char *wm_adsp_mem_region_name(unsigned int type) { switch (type) { case WMFW_ADSP1_PM: return "PM"; case WMFW_ADSP1_DM: return "DM"; case WMFW_ADSP2_XM: return "XM"; case WMFW_ADSP2_YM: return "YM"; case WMFW_ADSP1_ZM: return "ZM"; default: return NULL; } } #ifdef CONFIG_DEBUG_FS static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) { char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); kfree(dsp->wmfw_file_name); dsp->wmfw_file_name = tmp; } static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) { char *tmp = kasprintf(GFP_KERNEL, "%s\n", s); kfree(dsp->bin_file_name); dsp->bin_file_name = tmp; } static void wm_adsp_debugfs_clear(struct wm_adsp *dsp) { kfree(dsp->wmfw_file_name); kfree(dsp->bin_file_name); dsp->wmfw_file_name = NULL; dsp->bin_file_name = NULL; } static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { struct wm_adsp *dsp = file->private_data; ssize_t ret; mutex_lock(&dsp->pwr_lock); if (!dsp->wmfw_file_name || !dsp->booted) ret = 0; else ret = simple_read_from_buffer(user_buf, count, ppos, dsp->wmfw_file_name, strlen(dsp->wmfw_file_name)); mutex_unlock(&dsp->pwr_lock); return ret; } static ssize_t wm_adsp_debugfs_bin_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { struct wm_adsp *dsp = file->private_data; ssize_t ret; mutex_lock(&dsp->pwr_lock); if (!dsp->bin_file_name || !dsp->booted) ret = 0; else ret = simple_read_from_buffer(user_buf, count, ppos, dsp->bin_file_name, strlen(dsp->bin_file_name)); mutex_unlock(&dsp->pwr_lock); return ret; } static const struct { const char *name; const struct file_operations fops; } wm_adsp_debugfs_fops[] = { { .name = "wmfw_file_name", .fops = { .open = simple_open, .read = wm_adsp_debugfs_wmfw_read, }, }, { .name = "bin_file_name", .fops = { .open = simple_open, .read = wm_adsp_debugfs_bin_read, }, }, }; static void wm_adsp2_init_debugfs(struct wm_adsp *dsp, struct snd_soc_component *component) { struct dentry *root = NULL; int i; if (!component->debugfs_root) { adsp_err(dsp, "No codec debugfs root\n"); goto err; } root = debugfs_create_dir(dsp->name, component->debugfs_root); if (!root) goto err; if (!debugfs_create_bool("booted", 0444, root, &dsp->booted)) goto err; if (!debugfs_create_bool("running", 0444, root, &dsp->running)) goto err; if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id)) goto err; if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version)) goto err; for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) { if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name, 0444, root, dsp, &wm_adsp_debugfs_fops[i].fops)) goto err; } dsp->debugfs_root = root; return; err: debugfs_remove_recursive(root); adsp_err(dsp, "Failed to create debugfs\n"); } static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) { wm_adsp_debugfs_clear(dsp); debugfs_remove_recursive(dsp->debugfs_root); } #else static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp, struct snd_soc_component *component) { } static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp) { } static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s) { } static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s) { } static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp) { } #endif int wm_adsp_fw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw; return 0; } EXPORT_SYMBOL_GPL(wm_adsp_fw_get); int wm_adsp_fw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; struct wm_adsp *dsp = snd_soc_component_get_drvdata(component); int ret = 0; if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw) return 0; if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW) return -EINVAL; mutex_lock(&dsp[e->shift_l].pwr_lock); if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list)) ret = -EBUSY; else dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0]; mutex_unlock(&dsp[e->shift_l].pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp_fw_put); const struct soc_enum wm_adsp_fw_enum[] = { SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text), }; EXPORT_SYMBOL_GPL(wm_adsp_fw_enum); static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp, int type) { int i; for (i = 0; i < dsp->num_mems; i++) if (dsp->mem[i].type == type) return &dsp->mem[i]; return NULL; } static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem, unsigned int offset) { if (WARN_ON(!mem)) return offset; switch (mem->type) { case WMFW_ADSP1_PM: return mem->base + (offset * 3); case WMFW_ADSP1_DM: return mem->base + (offset * 2); case WMFW_ADSP2_XM: return mem->base + (offset * 2); case WMFW_ADSP2_YM: return mem->base + (offset * 2); case WMFW_ADSP1_ZM: return mem->base + (offset * 2); default: WARN(1, "Unknown memory region type"); return offset; } } static void wm_adsp2_show_fw_status(struct wm_adsp *dsp) { unsigned int scratch[4]; unsigned int addr = dsp->base + ADSP2_SCRATCH0; unsigned int i; int ret; for (i = 0; i < ARRAY_SIZE(scratch); ++i) { ret = regmap_read(dsp->regmap, addr + i, &scratch[i]); if (ret) { adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret); return; } } adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", scratch[0], scratch[1], scratch[2], scratch[3]); } static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp) { unsigned int scratch[2]; int ret; ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1, &scratch[0]); if (ret) { adsp_err(dsp, "Failed to read SCRATCH0_1: %d\n", ret); return; } ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH2_3, &scratch[1]); if (ret) { adsp_err(dsp, "Failed to read SCRATCH2_3: %d\n", ret); return; } adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n", scratch[0] & 0xFFFF, scratch[0] >> 16, scratch[1] & 0xFFFF, scratch[1] >> 16); } static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext) { return container_of(ext, struct wm_coeff_ctl, bytes_ext); } static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg) { const struct wm_adsp_alg_region *alg_region = &ctl->alg_region; struct wm_adsp *dsp = ctl->dsp; const struct wm_adsp_region *mem; mem = wm_adsp_find_region(dsp, alg_region->type); if (!mem) { adsp_err(dsp, "No base for region %x\n", alg_region->type); return -EINVAL; } *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset); return 0; } static int wm_coeff_info(struct snd_kcontrol *kctl, struct snd_ctl_elem_info *uinfo) { struct soc_bytes_ext *bytes_ext = (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); switch (ctl->type) { case WMFW_CTL_TYPE_ACKED: uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE; uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE; uinfo->value.integer.step = 1; uinfo->count = 1; break; default: uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; uinfo->count = ctl->len; break; } return 0; } static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl, unsigned int event_id) { struct wm_adsp *dsp = ctl->dsp; u32 val = cpu_to_be32(event_id); unsigned int reg; int i, ret; ret = wm_coeff_base_reg(ctl, ®); if (ret) return ret; adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n", event_id, ctl->alg_region.alg, wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val)); if (ret) { adsp_err(dsp, "Failed to write %x: %d\n", reg, ret); return ret; } /* * Poll for ack, we initially poll at ~1ms intervals for firmwares * that respond quickly, then go to ~10ms polls. A firmware is unlikely * to ack instantly so we do the first 1ms delay before reading the * control to avoid a pointless bus transaction */ for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) { switch (i) { case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1: usleep_range(1000, 2000); i++; break; default: usleep_range(10000, 20000); i += 10; break; } ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); if (ret) { adsp_err(dsp, "Failed to read %x: %d\n", reg, ret); return ret; } if (val == 0) { adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i); return 0; } } adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n", reg, ctl->alg_region.alg, wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset); return -ETIMEDOUT; } static int wm_coeff_write_control(struct wm_coeff_ctl *ctl, const void *buf, size_t len) { struct wm_adsp *dsp = ctl->dsp; void *scratch; int ret; unsigned int reg; ret = wm_coeff_base_reg(ctl, ®); if (ret) return ret; scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA); if (!scratch) return -ENOMEM; ret = regmap_raw_write(dsp->regmap, reg, scratch, len); if (ret) { adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n", len, reg, ret); kfree(scratch); return ret; } adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg); kfree(scratch); return 0; } static int wm_coeff_put(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) { struct soc_bytes_ext *bytes_ext = (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); char *p = ucontrol->value.bytes.data; int ret = 0; mutex_lock(&ctl->dsp->pwr_lock); if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) ret = -EPERM; else memcpy(ctl->cache, p, ctl->len); ctl->set = 1; if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_write_control(ctl, p, ctl->len); mutex_unlock(&ctl->dsp->pwr_lock); return ret; } static int wm_coeff_tlv_put(struct snd_kcontrol *kctl, const unsigned int __user *bytes, unsigned int size) { struct soc_bytes_ext *bytes_ext = (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); int ret = 0; mutex_lock(&ctl->dsp->pwr_lock); if (copy_from_user(ctl->cache, bytes, size)) { ret = -EFAULT; } else { ctl->set = 1; if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_write_control(ctl, ctl->cache, size); else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) ret = -EPERM; } mutex_unlock(&ctl->dsp->pwr_lock); return ret; } static int wm_coeff_put_acked(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) { struct soc_bytes_ext *bytes_ext = (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); unsigned int val = ucontrol->value.integer.value[0]; int ret; if (val == 0) return 0; /* 0 means no event */ mutex_lock(&ctl->dsp->pwr_lock); if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_write_acked_control(ctl, val); else ret = -EPERM; mutex_unlock(&ctl->dsp->pwr_lock); return ret; } static int wm_coeff_read_control(struct wm_coeff_ctl *ctl, void *buf, size_t len) { struct wm_adsp *dsp = ctl->dsp; void *scratch; int ret; unsigned int reg; ret = wm_coeff_base_reg(ctl, ®); if (ret) return ret; scratch = kmalloc(len, GFP_KERNEL | GFP_DMA); if (!scratch) return -ENOMEM; ret = regmap_raw_read(dsp->regmap, reg, scratch, len); if (ret) { adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n", len, reg, ret); kfree(scratch); return ret; } adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg); memcpy(buf, scratch, len); kfree(scratch); return 0; } static int wm_coeff_get(struct snd_kcontrol *kctl, struct snd_ctl_elem_value *ucontrol) { struct soc_bytes_ext *bytes_ext = (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); char *p = ucontrol->value.bytes.data; int ret = 0; mutex_lock(&ctl->dsp->pwr_lock); if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, p, ctl->len); else ret = -EPERM; } else { if (!ctl->flags && ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); memcpy(p, ctl->cache, ctl->len); } mutex_unlock(&ctl->dsp->pwr_lock); return ret; } static int wm_coeff_tlv_get(struct snd_kcontrol *kctl, unsigned int __user *bytes, unsigned int size) { struct soc_bytes_ext *bytes_ext = (struct soc_bytes_ext *)kctl->private_value; struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext); int ret = 0; mutex_lock(&ctl->dsp->pwr_lock); if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) { if (ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, ctl->cache, size); else ret = -EPERM; } else { if (!ctl->flags && ctl->enabled && ctl->dsp->running) ret = wm_coeff_read_control(ctl, ctl->cache, size); } if (!ret && copy_to_user(bytes, ctl->cache, size)) ret = -EFAULT; mutex_unlock(&ctl->dsp->pwr_lock); return ret; } static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { /* * Although it's not useful to read an acked control, we must satisfy * user-side assumptions that all controls are readable and that a * write of the same value should be filtered out (it's valid to send * the same event number again to the firmware). We therefore return 0, * meaning "no event" so valid event numbers will always be a change */ ucontrol->value.integer.value[0] = 0; return 0; } struct wmfw_ctl_work { struct wm_adsp *dsp; struct wm_coeff_ctl *ctl; struct work_struct work; }; static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len) { unsigned int out, rd, wr, vol; if (len > ADSP_MAX_STD_CTRL_SIZE) { rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ; wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE; vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK; } else { rd = SNDRV_CTL_ELEM_ACCESS_READ; wr = SNDRV_CTL_ELEM_ACCESS_WRITE; vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE; out = 0; } if (in) { if (in & WMFW_CTL_FLAG_READABLE) out |= rd; if (in & WMFW_CTL_FLAG_WRITEABLE) out |= wr; if (in & WMFW_CTL_FLAG_VOLATILE) out |= vol; } else { out |= rd | wr | vol; } return out; } static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl) { struct snd_kcontrol_new *kcontrol; int ret; if (!ctl || !ctl->name) return -EINVAL; kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL); if (!kcontrol) return -ENOMEM; kcontrol->name = ctl->name; kcontrol->info = wm_coeff_info; kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER; kcontrol->tlv.c = snd_soc_bytes_tlv_callback; kcontrol->private_value = (unsigned long)&ctl->bytes_ext; kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len); switch (ctl->type) { case WMFW_CTL_TYPE_ACKED: kcontrol->get = wm_coeff_get_acked; kcontrol->put = wm_coeff_put_acked; break; default: if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { ctl->bytes_ext.max = ctl->len; ctl->bytes_ext.get = wm_coeff_tlv_get; ctl->bytes_ext.put = wm_coeff_tlv_put; } else { kcontrol->get = wm_coeff_get; kcontrol->put = wm_coeff_put; } break; } ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1); if (ret < 0) goto err_kcontrol; kfree(kcontrol); return 0; err_kcontrol: kfree(kcontrol); return ret; } static int wm_coeff_init_control_caches(struct wm_adsp *dsp) { struct wm_coeff_ctl *ctl; int ret; list_for_each_entry(ctl, &dsp->ctl_list, list) { if (!ctl->enabled || ctl->set) continue; if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) continue; /* * For readable controls populate the cache from the DSP memory. * For non-readable controls the cache was zero-filled when * created so we don't need to do anything. */ if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) { ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len); if (ret < 0) return ret; } } return 0; } static int wm_coeff_sync_controls(struct wm_adsp *dsp) { struct wm_coeff_ctl *ctl; int ret; list_for_each_entry(ctl, &dsp->ctl_list, list) { if (!ctl->enabled) continue; if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) { ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len); if (ret < 0) return ret; } } return 0; } static void wm_adsp_signal_event_controls(struct wm_adsp *dsp, unsigned int event) { struct wm_coeff_ctl *ctl; int ret; list_for_each_entry(ctl, &dsp->ctl_list, list) { if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT) continue; if (!ctl->enabled) continue; ret = wm_coeff_write_acked_control(ctl, event); if (ret) adsp_warn(dsp, "Failed to send 0x%x event to alg 0x%x (%d)\n", event, ctl->alg_region.alg, ret); } } static void wm_adsp_ctl_work(struct work_struct *work) { struct wmfw_ctl_work *ctl_work = container_of(work, struct wmfw_ctl_work, work); wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl); kfree(ctl_work); } static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl) { kfree(ctl->cache); kfree(ctl->name); kfree(ctl); } static int wm_adsp_create_control(struct wm_adsp *dsp, const struct wm_adsp_alg_region *alg_region, unsigned int offset, unsigned int len, const char *subname, unsigned int subname_len, unsigned int flags, unsigned int type) { struct wm_coeff_ctl *ctl; struct wmfw_ctl_work *ctl_work; char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; const char *region_name; int ret; region_name = wm_adsp_mem_region_name(alg_region->type); if (!region_name) { adsp_err(dsp, "Unknown region type: %d\n", alg_region->type); return -EINVAL; } switch (dsp->fw_ver) { case 0: case 1: snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x", dsp->name, region_name, alg_region->alg); break; default: ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s%c %.12s %x", dsp->name, *region_name, wm_adsp_fw_text[dsp->fw], alg_region->alg); /* Truncate the subname from the start if it is too long */ if (subname) { int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2; int skip = 0; if (dsp->component->name_prefix) avail -= strlen(dsp->component->name_prefix) + 1; if (subname_len > avail) skip = subname_len - avail; snprintf(name + ret, SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s", subname_len - skip, subname + skip); } break; } list_for_each_entry(ctl, &dsp->ctl_list, list) { if (!strcmp(ctl->name, name)) { if (!ctl->enabled) ctl->enabled = 1; return 0; } } ctl = kzalloc(sizeof(*ctl), GFP_KERNEL); if (!ctl) return -ENOMEM; ctl->fw_name = wm_adsp_fw_text[dsp->fw]; ctl->alg_region = *alg_region; ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL); if (!ctl->name) { ret = -ENOMEM; goto err_ctl; } ctl->enabled = 1; ctl->set = 0; ctl->ops.xget = wm_coeff_get; ctl->ops.xput = wm_coeff_put; ctl->dsp = dsp; ctl->flags = flags; ctl->type = type; ctl->offset = offset; ctl->len = len; ctl->cache = kzalloc(ctl->len, GFP_KERNEL); if (!ctl->cache) { ret = -ENOMEM; goto err_ctl_name; } list_add(&ctl->list, &dsp->ctl_list); if (flags & WMFW_CTL_FLAG_SYS) return 0; ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL); if (!ctl_work) { ret = -ENOMEM; goto err_ctl_cache; } ctl_work->dsp = dsp; ctl_work->ctl = ctl; INIT_WORK(&ctl_work->work, wm_adsp_ctl_work); schedule_work(&ctl_work->work); return 0; err_ctl_cache: kfree(ctl->cache); err_ctl_name: kfree(ctl->name); err_ctl: kfree(ctl); return ret; } struct wm_coeff_parsed_alg { int id; const u8 *name; int name_len; int ncoeff; }; struct wm_coeff_parsed_coeff { int offset; int mem_type; const u8 *name; int name_len; int ctl_type; int flags; int len; }; static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str) { int length; switch (bytes) { case 1: length = **pos; break; case 2: length = le16_to_cpu(*((__le16 *)*pos)); break; default: return 0; } if (str) *str = *pos + bytes; *pos += ((length + bytes) + 3) & ~0x03; return length; } static int wm_coeff_parse_int(int bytes, const u8 **pos) { int val = 0; switch (bytes) { case 2: val = le16_to_cpu(*((__le16 *)*pos)); break; case 4: val = le32_to_cpu(*((__le32 *)*pos)); break; default: break; } *pos += bytes; return val; } static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data, struct wm_coeff_parsed_alg *blk) { const struct wmfw_adsp_alg_data *raw; switch (dsp->fw_ver) { case 0: case 1: raw = (const struct wmfw_adsp_alg_data *)*data; *data = raw->data; blk->id = le32_to_cpu(raw->id); blk->name = raw->name; blk->name_len = strlen(raw->name); blk->ncoeff = le32_to_cpu(raw->ncoeff); break; default: blk->id = wm_coeff_parse_int(sizeof(raw->id), data); blk->name_len = wm_coeff_parse_string(sizeof(u8), data, &blk->name); wm_coeff_parse_string(sizeof(u16), data, NULL); blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data); break; } adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id); adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name); adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff); } static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data, struct wm_coeff_parsed_coeff *blk) { const struct wmfw_adsp_coeff_data *raw; const u8 *tmp; int length; switch (dsp->fw_ver) { case 0: case 1: raw = (const struct wmfw_adsp_coeff_data *)*data; *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size); blk->offset = le16_to_cpu(raw->hdr.offset); blk->mem_type = le16_to_cpu(raw->hdr.type); blk->name = raw->name; blk->name_len = strlen(raw->name); blk->ctl_type = le16_to_cpu(raw->ctl_type); blk->flags = le16_to_cpu(raw->flags); blk->len = le32_to_cpu(raw->len); break; default: tmp = *data; blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp); blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp); length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp); blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp, &blk->name); wm_coeff_parse_string(sizeof(u8), &tmp, NULL); wm_coeff_parse_string(sizeof(u16), &tmp, NULL); blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp); blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp); blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp); *data = *data + sizeof(raw->hdr) + length; break; } adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type); adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset); adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name); adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags); adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type); adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len); } static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp, const struct wm_coeff_parsed_coeff *coeff_blk, unsigned int f_required, unsigned int f_illegal) { if ((coeff_blk->flags & f_illegal) || ((coeff_blk->flags & f_required) != f_required)) { adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n", coeff_blk->flags, coeff_blk->ctl_type); return -EINVAL; } return 0; } static int wm_adsp_parse_coeff(struct wm_adsp *dsp, const struct wmfw_region *region) { struct wm_adsp_alg_region alg_region = {}; struct wm_coeff_parsed_alg alg_blk; struct wm_coeff_parsed_coeff coeff_blk; const u8 *data = region->data; int i, ret; wm_coeff_parse_alg(dsp, &data, &alg_blk); for (i = 0; i < alg_blk.ncoeff; i++) { wm_coeff_parse_coeff(dsp, &data, &coeff_blk); switch (coeff_blk.ctl_type) { case SNDRV_CTL_ELEM_TYPE_BYTES: break; case WMFW_CTL_TYPE_ACKED: if (coeff_blk.flags & WMFW_CTL_FLAG_SYS) continue; /* ignore */ ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, WMFW_CTL_FLAG_VOLATILE | WMFW_CTL_FLAG_WRITEABLE | WMFW_CTL_FLAG_READABLE, 0); if (ret) return -EINVAL; break; case WMFW_CTL_TYPE_HOSTEVENT: ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, WMFW_CTL_FLAG_SYS | WMFW_CTL_FLAG_VOLATILE | WMFW_CTL_FLAG_WRITEABLE | WMFW_CTL_FLAG_READABLE, 0); if (ret) return -EINVAL; break; case WMFW_CTL_TYPE_HOST_BUFFER: ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk, WMFW_CTL_FLAG_SYS | WMFW_CTL_FLAG_VOLATILE | WMFW_CTL_FLAG_READABLE, 0); if (ret) return -EINVAL; break; default: adsp_err(dsp, "Unknown control type: %d\n", coeff_blk.ctl_type); return -EINVAL; } alg_region.type = coeff_blk.mem_type; alg_region.alg = alg_blk.id; ret = wm_adsp_create_control(dsp, &alg_region, coeff_blk.offset, coeff_blk.len, coeff_blk.name, coeff_blk.name_len, coeff_blk.flags, coeff_blk.ctl_type); if (ret < 0) adsp_err(dsp, "Failed to create control: %.*s, %d\n", coeff_blk.name_len, coeff_blk.name, ret); } return 0; } static int wm_adsp_load(struct wm_adsp *dsp) { LIST_HEAD(buf_list); const struct firmware *firmware; struct regmap *regmap = dsp->regmap; unsigned int pos = 0; const struct wmfw_header *header; const struct wmfw_adsp1_sizes *adsp1_sizes; const struct wmfw_adsp2_sizes *adsp2_sizes; const struct wmfw_footer *footer; const struct wmfw_region *region; const struct wm_adsp_region *mem; const char *region_name; char *file, *text = NULL; struct wm_adsp_buf *buf; unsigned int reg; int regions = 0; int ret, offset, type, sizes; file = kzalloc(PAGE_SIZE, GFP_KERNEL); if (file == NULL) return -ENOMEM; snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name, wm_adsp_fw[dsp->fw].file); file[PAGE_SIZE - 1] = '\0'; ret = request_firmware(&firmware, file, dsp->dev); if (ret != 0) { adsp_err(dsp, "Failed to request '%s'\n", file); goto out; } ret = -EINVAL; pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); if (pos >= firmware->size) { adsp_err(dsp, "%s: file too short, %zu bytes\n", file, firmware->size); goto out_fw; } header = (void *)&firmware->data[0]; if (memcmp(&header->magic[0], "WMFW", 4) != 0) { adsp_err(dsp, "%s: invalid magic\n", file); goto out_fw; } switch (header->ver) { case 0: adsp_warn(dsp, "%s: Depreciated file format %d\n", file, header->ver); break; case 1: case 2: break; default: adsp_err(dsp, "%s: unknown file format %d\n", file, header->ver); goto out_fw; } adsp_info(dsp, "Firmware version: %d\n", header->ver); dsp->fw_ver = header->ver; if (header->core != dsp->type) { adsp_err(dsp, "%s: invalid core %d != %d\n", file, header->core, dsp->type); goto out_fw; } switch (dsp->type) { case WMFW_ADSP1: pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer); adsp1_sizes = (void *)&(header[1]); footer = (void *)&(adsp1_sizes[1]); sizes = sizeof(*adsp1_sizes); adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n", file, le32_to_cpu(adsp1_sizes->dm), le32_to_cpu(adsp1_sizes->pm), le32_to_cpu(adsp1_sizes->zm)); break; case WMFW_ADSP2: pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer); adsp2_sizes = (void *)&(header[1]); footer = (void *)&(adsp2_sizes[1]); sizes = sizeof(*adsp2_sizes); adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n", file, le32_to_cpu(adsp2_sizes->xm), le32_to_cpu(adsp2_sizes->ym), le32_to_cpu(adsp2_sizes->pm), le32_to_cpu(adsp2_sizes->zm)); break; default: WARN(1, "Unknown DSP type"); goto out_fw; } if (le32_to_cpu(header->len) != sizeof(*header) + sizes + sizeof(*footer)) { adsp_err(dsp, "%s: unexpected header length %d\n", file, le32_to_cpu(header->len)); goto out_fw; } adsp_dbg(dsp, "%s: timestamp %llu\n", file, le64_to_cpu(footer->timestamp)); while (pos < firmware->size && sizeof(*region) < firmware->size - pos) { region = (void *)&(firmware->data[pos]); region_name = "Unknown"; reg = 0; text = NULL; offset = le32_to_cpu(region->offset) & 0xffffff; type = be32_to_cpu(region->type) & 0xff; mem = wm_adsp_find_region(dsp, type); switch (type) { case WMFW_NAME_TEXT: region_name = "Firmware name"; text = kzalloc(le32_to_cpu(region->len) + 1, GFP_KERNEL); break; case WMFW_ALGORITHM_DATA: region_name = "Algorithm"; ret = wm_adsp_parse_coeff(dsp, region); if (ret != 0) goto out_fw; break; case WMFW_INFO_TEXT: region_name = "Information"; text = kzalloc(le32_to_cpu(region->len) + 1, GFP_KERNEL); break; case WMFW_ABSOLUTE: region_name = "Absolute"; reg = offset; break; case WMFW_ADSP1_PM: case WMFW_ADSP1_DM: case WMFW_ADSP2_XM: case WMFW_ADSP2_YM: case WMFW_ADSP1_ZM: region_name = wm_adsp_mem_region_name(type); reg = wm_adsp_region_to_reg(mem, offset); break; default: adsp_warn(dsp, "%s.%d: Unknown region type %x at %d(%x)\n", file, regions, type, pos, pos); break; } adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file, regions, le32_to_cpu(region->len), offset, region_name); if (le32_to_cpu(region->len) > firmware->size - pos - sizeof(*region)) { adsp_err(dsp, "%s.%d: %s region len %d bytes exceeds file length %zu\n", file, regions, region_name, le32_to_cpu(region->len), firmware->size); ret = -EINVAL; goto out_fw; } if (text) { memcpy(text, region->data, le32_to_cpu(region->len)); adsp_info(dsp, "%s: %s\n", file, text); kfree(text); text = NULL; } if (reg) { buf = wm_adsp_buf_alloc(region->data, le32_to_cpu(region->len), &buf_list); if (!buf) { adsp_err(dsp, "Out of memory\n"); ret = -ENOMEM; goto out_fw; } ret = regmap_raw_write_async(regmap, reg, buf->buf, le32_to_cpu(region->len)); if (ret != 0) { adsp_err(dsp, "%s.%d: Failed to write %d bytes at %d in %s: %d\n", file, regions, le32_to_cpu(region->len), offset, region_name, ret); goto out_fw; } } pos += le32_to_cpu(region->len) + sizeof(*region); regions++; } ret = regmap_async_complete(regmap); if (ret != 0) { adsp_err(dsp, "Failed to complete async write: %d\n", ret); goto out_fw; } if (pos > firmware->size) adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, regions, pos - firmware->size); wm_adsp_debugfs_save_wmfwname(dsp, file); out_fw: regmap_async_complete(regmap); wm_adsp_buf_free(&buf_list); release_firmware(firmware); kfree(text); out: kfree(file); return ret; } static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp, const struct wm_adsp_alg_region *alg_region) { struct wm_coeff_ctl *ctl; list_for_each_entry(ctl, &dsp->ctl_list, list) { if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] && alg_region->alg == ctl->alg_region.alg && alg_region->type == ctl->alg_region.type) { ctl->alg_region.base = alg_region->base; } } } static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs, const struct wm_adsp_region *mem, unsigned int pos, unsigned int len) { void *alg; unsigned int reg; int ret; __be32 val; if (n_algs == 0) { adsp_err(dsp, "No algorithms\n"); return ERR_PTR(-EINVAL); } if (n_algs > 1024) { adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs); return ERR_PTR(-EINVAL); } /* Read the terminator first to validate the length */ reg = wm_adsp_region_to_reg(mem, pos + len); ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val)); if (ret != 0) { adsp_err(dsp, "Failed to read algorithm list end: %d\n", ret); return ERR_PTR(ret); } if (be32_to_cpu(val) != 0xbedead) adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n", reg, be32_to_cpu(val)); /* Convert length from DSP words to bytes */ len *= sizeof(u32); alg = kzalloc(len, GFP_KERNEL | GFP_DMA); if (!alg) return ERR_PTR(-ENOMEM); reg = wm_adsp_region_to_reg(mem, pos); ret = regmap_raw_read(dsp->regmap, reg, alg, len); if (ret != 0) { adsp_err(dsp, "Failed to read algorithm list: %d\n", ret); kfree(alg); return ERR_PTR(ret); } return alg; } static struct wm_adsp_alg_region * wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id) { struct wm_adsp_alg_region *alg_region; list_for_each_entry(alg_region, &dsp->alg_regions, list) { if (id == alg_region->alg && type == alg_region->type) return alg_region; } return NULL; } static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp, int type, __be32 id, __be32 base) { struct wm_adsp_alg_region *alg_region; alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL); if (!alg_region) return ERR_PTR(-ENOMEM); alg_region->type = type; alg_region->alg = be32_to_cpu(id); alg_region->base = be32_to_cpu(base); list_add_tail(&alg_region->list, &dsp->alg_regions); if (dsp->fw_ver > 0) wm_adsp_ctl_fixup_base(dsp, alg_region); return alg_region; } static void wm_adsp_free_alg_regions(struct wm_adsp *dsp) { struct wm_adsp_alg_region *alg_region; while (!list_empty(&dsp->alg_regions)) { alg_region = list_first_entry(&dsp->alg_regions, struct wm_adsp_alg_region, list); list_del(&alg_region->list); kfree(alg_region); } } static int wm_adsp1_setup_algs(struct wm_adsp *dsp) { struct wmfw_adsp1_id_hdr adsp1_id; struct wmfw_adsp1_alg_hdr *adsp1_alg; struct wm_adsp_alg_region *alg_region; const struct wm_adsp_region *mem; unsigned int pos, len; size_t n_algs; int i, ret; mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM); if (WARN_ON(!mem)) return -EINVAL; ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id, sizeof(adsp1_id)); if (ret != 0) { adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); return ret; } n_algs = be32_to_cpu(adsp1_id.n_algs); dsp->fw_id = be32_to_cpu(adsp1_id.fw.id); adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", dsp->fw_id, (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16, (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8, be32_to_cpu(adsp1_id.fw.ver) & 0xff, n_algs); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, adsp1_id.fw.id, adsp1_id.zm); if (IS_ERR(alg_region)) return PTR_ERR(alg_region); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, adsp1_id.fw.id, adsp1_id.dm); if (IS_ERR(alg_region)) return PTR_ERR(alg_region); /* Calculate offset and length in DSP words */ pos = sizeof(adsp1_id) / sizeof(u32); len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32); adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); if (IS_ERR(adsp1_alg)) return PTR_ERR(adsp1_alg); for (i = 0; i < n_algs; i++) { adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n", i, be32_to_cpu(adsp1_alg[i].alg.id), (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16, (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8, be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff, be32_to_cpu(adsp1_alg[i].dm), be32_to_cpu(adsp1_alg[i].zm)); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM, adsp1_alg[i].alg.id, adsp1_alg[i].dm); if (IS_ERR(alg_region)) { ret = PTR_ERR(alg_region); goto out; } if (dsp->fw_ver == 0) { if (i + 1 < n_algs) { len = be32_to_cpu(adsp1_alg[i + 1].dm); len -= be32_to_cpu(adsp1_alg[i].dm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, len, NULL, 0, 0, SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region DM with ID %x\n", be32_to_cpu(adsp1_alg[i].alg.id)); } } alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM, adsp1_alg[i].alg.id, adsp1_alg[i].zm); if (IS_ERR(alg_region)) { ret = PTR_ERR(alg_region); goto out; } if (dsp->fw_ver == 0) { if (i + 1 < n_algs) { len = be32_to_cpu(adsp1_alg[i + 1].zm); len -= be32_to_cpu(adsp1_alg[i].zm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, len, NULL, 0, 0, SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", be32_to_cpu(adsp1_alg[i].alg.id)); } } } out: kfree(adsp1_alg); return ret; } static int wm_adsp2_setup_algs(struct wm_adsp *dsp) { struct wmfw_adsp2_id_hdr adsp2_id; struct wmfw_adsp2_alg_hdr *adsp2_alg; struct wm_adsp_alg_region *alg_region; const struct wm_adsp_region *mem; unsigned int pos, len; size_t n_algs; int i, ret; mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM); if (WARN_ON(!mem)) return -EINVAL; ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id, sizeof(adsp2_id)); if (ret != 0) { adsp_err(dsp, "Failed to read algorithm info: %d\n", ret); return ret; } n_algs = be32_to_cpu(adsp2_id.n_algs); dsp->fw_id = be32_to_cpu(adsp2_id.fw.id); dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver); adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n", dsp->fw_id, (dsp->fw_id_version & 0xff0000) >> 16, (dsp->fw_id_version & 0xff00) >> 8, dsp->fw_id_version & 0xff, n_algs); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, adsp2_id.fw.id, adsp2_id.xm); if (IS_ERR(alg_region)) return PTR_ERR(alg_region); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, adsp2_id.fw.id, adsp2_id.ym); if (IS_ERR(alg_region)) return PTR_ERR(alg_region); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, adsp2_id.fw.id, adsp2_id.zm); if (IS_ERR(alg_region)) return PTR_ERR(alg_region); /* Calculate offset and length in DSP words */ pos = sizeof(adsp2_id) / sizeof(u32); len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32); adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len); if (IS_ERR(adsp2_alg)) return PTR_ERR(adsp2_alg); for (i = 0; i < n_algs; i++) { adsp_info(dsp, "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n", i, be32_to_cpu(adsp2_alg[i].alg.id), (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16, (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8, be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff, be32_to_cpu(adsp2_alg[i].xm), be32_to_cpu(adsp2_alg[i].ym), be32_to_cpu(adsp2_alg[i].zm)); alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM, adsp2_alg[i].alg.id, adsp2_alg[i].xm); if (IS_ERR(alg_region)) { ret = PTR_ERR(alg_region); goto out; } if (dsp->fw_ver == 0) { if (i + 1 < n_algs) { len = be32_to_cpu(adsp2_alg[i + 1].xm); len -= be32_to_cpu(adsp2_alg[i].xm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, len, NULL, 0, 0, SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region XM with ID %x\n", be32_to_cpu(adsp2_alg[i].alg.id)); } } alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM, adsp2_alg[i].alg.id, adsp2_alg[i].ym); if (IS_ERR(alg_region)) { ret = PTR_ERR(alg_region); goto out; } if (dsp->fw_ver == 0) { if (i + 1 < n_algs) { len = be32_to_cpu(adsp2_alg[i + 1].ym); len -= be32_to_cpu(adsp2_alg[i].ym); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, len, NULL, 0, 0, SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region YM with ID %x\n", be32_to_cpu(adsp2_alg[i].alg.id)); } } alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM, adsp2_alg[i].alg.id, adsp2_alg[i].zm); if (IS_ERR(alg_region)) { ret = PTR_ERR(alg_region); goto out; } if (dsp->fw_ver == 0) { if (i + 1 < n_algs) { len = be32_to_cpu(adsp2_alg[i + 1].zm); len -= be32_to_cpu(adsp2_alg[i].zm); len *= 4; wm_adsp_create_control(dsp, alg_region, 0, len, NULL, 0, 0, SNDRV_CTL_ELEM_TYPE_BYTES); } else { adsp_warn(dsp, "Missing length info for region ZM with ID %x\n", be32_to_cpu(adsp2_alg[i].alg.id)); } } } out: kfree(adsp2_alg); return ret; } static int wm_adsp_load_coeff(struct wm_adsp *dsp) { LIST_HEAD(buf_list); struct regmap *regmap = dsp->regmap; struct wmfw_coeff_hdr *hdr; struct wmfw_coeff_item *blk; const struct firmware *firmware; const struct wm_adsp_region *mem; struct wm_adsp_alg_region *alg_region; const char *region_name; int ret, pos, blocks, type, offset, reg; char *file; struct wm_adsp_buf *buf; file = kzalloc(PAGE_SIZE, GFP_KERNEL); if (file == NULL) return -ENOMEM; snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name, wm_adsp_fw[dsp->fw].file); file[PAGE_SIZE - 1] = '\0'; ret = request_firmware(&firmware, file, dsp->dev); if (ret != 0) { adsp_warn(dsp, "Failed to request '%s'\n", file); ret = 0; goto out; } ret = -EINVAL; if (sizeof(*hdr) >= firmware->size) { adsp_err(dsp, "%s: file too short, %zu bytes\n", file, firmware->size); goto out_fw; } hdr = (void *)&firmware->data[0]; if (memcmp(hdr->magic, "WMDR", 4) != 0) { adsp_err(dsp, "%s: invalid magic\n", file); goto out_fw; } switch (be32_to_cpu(hdr->rev) & 0xff) { case 1: break; default: adsp_err(dsp, "%s: Unsupported coefficient file format %d\n", file, be32_to_cpu(hdr->rev) & 0xff); ret = -EINVAL; goto out_fw; } adsp_dbg(dsp, "%s: v%d.%d.%d\n", file, (le32_to_cpu(hdr->ver) >> 16) & 0xff, (le32_to_cpu(hdr->ver) >> 8) & 0xff, le32_to_cpu(hdr->ver) & 0xff); pos = le32_to_cpu(hdr->len); blocks = 0; while (pos < firmware->size && sizeof(*blk) < firmware->size - pos) { blk = (void *)(&firmware->data[pos]); type = le16_to_cpu(blk->type); offset = le16_to_cpu(blk->offset); adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n", file, blocks, le32_to_cpu(blk->id), (le32_to_cpu(blk->ver) >> 16) & 0xff, (le32_to_cpu(blk->ver) >> 8) & 0xff, le32_to_cpu(blk->ver) & 0xff); adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n", file, blocks, le32_to_cpu(blk->len), offset, type); reg = 0; region_name = "Unknown"; switch (type) { case (WMFW_NAME_TEXT << 8): case (WMFW_INFO_TEXT << 8): break; case (WMFW_ABSOLUTE << 8): /* * Old files may use this for global * coefficients. */ if (le32_to_cpu(blk->id) == dsp->fw_id && offset == 0) { region_name = "global coefficients"; mem = wm_adsp_find_region(dsp, type); if (!mem) { adsp_err(dsp, "No ZM\n"); break; } reg = wm_adsp_region_to_reg(mem, 0); } else { region_name = "register"; reg = offset; } break; case WMFW_ADSP1_DM: case WMFW_ADSP1_ZM: case WMFW_ADSP2_XM: case WMFW_ADSP2_YM: adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n", file, blocks, le32_to_cpu(blk->len), type, le32_to_cpu(blk->id)); mem = wm_adsp_find_region(dsp, type); if (!mem) { adsp_err(dsp, "No base for region %x\n", type); break; } alg_region = wm_adsp_find_alg_region(dsp, type, le32_to_cpu(blk->id)); if (alg_region) { reg = alg_region->base; reg = wm_adsp_region_to_reg(mem, reg); reg += offset; } else { adsp_err(dsp, "No %x for algorithm %x\n", type, le32_to_cpu(blk->id)); } break; default: adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n", file, blocks, type, pos); break; } if (reg) { if (le32_to_cpu(blk->len) > firmware->size - pos - sizeof(*blk)) { adsp_err(dsp, "%s.%d: %s region len %d bytes exceeds file length %zu\n", file, blocks, region_name, le32_to_cpu(blk->len), firmware->size); ret = -EINVAL; goto out_fw; } buf = wm_adsp_buf_alloc(blk->data, le32_to_cpu(blk->len), &buf_list); if (!buf) { adsp_err(dsp, "Out of memory\n"); ret = -ENOMEM; goto out_fw; } adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n", file, blocks, le32_to_cpu(blk->len), reg); ret = regmap_raw_write_async(regmap, reg, buf->buf, le32_to_cpu(blk->len)); if (ret != 0) { adsp_err(dsp, "%s.%d: Failed to write to %x in %s: %d\n", file, blocks, reg, region_name, ret); } } pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03; blocks++; } ret = regmap_async_complete(regmap); if (ret != 0) adsp_err(dsp, "Failed to complete async write: %d\n", ret); if (pos > firmware->size) adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n", file, blocks, pos - firmware->size); wm_adsp_debugfs_save_binname(dsp, file); out_fw: regmap_async_complete(regmap); release_firmware(firmware); wm_adsp_buf_free(&buf_list); out: kfree(file); return ret; } static int wm_adsp_create_name(struct wm_adsp *dsp) { char *p; if (!dsp->name) { dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d", dsp->num); if (!dsp->name) return -ENOMEM; } if (!dsp->fwf_name) { p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL); if (!p) return -ENOMEM; dsp->fwf_name = p; for (; *p != 0; ++p) *p = tolower(*p); } return 0; } static int wm_adsp_common_init(struct wm_adsp *dsp) { int ret; ret = wm_adsp_create_name(dsp); if (ret) return ret; INIT_LIST_HEAD(&dsp->alg_regions); INIT_LIST_HEAD(&dsp->ctl_list); INIT_LIST_HEAD(&dsp->compr_list); INIT_LIST_HEAD(&dsp->buffer_list); mutex_init(&dsp->pwr_lock); return 0; } int wm_adsp1_init(struct wm_adsp *dsp) { return wm_adsp_common_init(dsp); } EXPORT_SYMBOL_GPL(wm_adsp1_init); int wm_adsp1_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); struct wm_adsp *dsp = &dsps[w->shift]; struct wm_coeff_ctl *ctl; int ret; unsigned int val; dsp->component = component; mutex_lock(&dsp->pwr_lock); switch (event) { case SND_SOC_DAPM_POST_PMU: regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_SYS_ENA, ADSP1_SYS_ENA); /* * For simplicity set the DSP clock rate to be the * SYSCLK rate rather than making it configurable. */ if (dsp->sysclk_reg) { ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val); if (ret != 0) { adsp_err(dsp, "Failed to read SYSCLK state: %d\n", ret); goto err_mutex; } val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift; ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_31, ADSP1_CLK_SEL_MASK, val); if (ret != 0) { adsp_err(dsp, "Failed to set clock rate: %d\n", ret); goto err_mutex; } } ret = wm_adsp_load(dsp); if (ret != 0) goto err_ena; ret = wm_adsp1_setup_algs(dsp); if (ret != 0) goto err_ena; ret = wm_adsp_load_coeff(dsp); if (ret != 0) goto err_ena; /* Initialize caches for enabled and unset controls */ ret = wm_coeff_init_control_caches(dsp); if (ret != 0) goto err_ena; /* Sync set controls */ ret = wm_coeff_sync_controls(dsp); if (ret != 0) goto err_ena; dsp->booted = true; /* Start the core running */ regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_CORE_ENA | ADSP1_START, ADSP1_CORE_ENA | ADSP1_START); dsp->running = true; break; case SND_SOC_DAPM_PRE_PMD: dsp->running = false; dsp->booted = false; /* Halt the core */ regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_CORE_ENA | ADSP1_START, 0); regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19, ADSP1_WDMA_BUFFER_LENGTH_MASK, 0); regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_SYS_ENA, 0); list_for_each_entry(ctl, &dsp->ctl_list, list) ctl->enabled = 0; wm_adsp_free_alg_regions(dsp); break; default: break; } mutex_unlock(&dsp->pwr_lock); return 0; err_ena: regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30, ADSP1_SYS_ENA, 0); err_mutex: mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp1_event); static int wm_adsp2_ena(struct wm_adsp *dsp) { unsigned int val; int ret, count; switch (dsp->rev) { case 0: ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA, ADSP2_SYS_ENA); if (ret != 0) return ret; break; default: break; } /* Wait for the RAM to start, should be near instantaneous */ for (count = 0; count < 10; ++count) { ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val); if (ret != 0) return ret; if (val & ADSP2_RAM_RDY) break; usleep_range(250, 500); } if (!(val & ADSP2_RAM_RDY)) { adsp_err(dsp, "Failed to start DSP RAM\n"); return -EBUSY; } adsp_dbg(dsp, "RAM ready after %d polls\n", count); return 0; } static void wm_adsp2_boot_work(struct work_struct *work) { struct wm_adsp *dsp = container_of(work, struct wm_adsp, boot_work); int ret; mutex_lock(&dsp->pwr_lock); ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_MEM_ENA, ADSP2_MEM_ENA); if (ret != 0) goto err_mutex; ret = wm_adsp2_ena(dsp); if (ret != 0) goto err_mem; ret = wm_adsp_load(dsp); if (ret != 0) goto err_ena; ret = wm_adsp2_setup_algs(dsp); if (ret != 0) goto err_ena; ret = wm_adsp_load_coeff(dsp); if (ret != 0) goto err_ena; /* Initialize caches for enabled and unset controls */ ret = wm_coeff_init_control_caches(dsp); if (ret != 0) goto err_ena; switch (dsp->rev) { case 0: /* Turn DSP back off until we are ready to run */ ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA, 0); if (ret != 0) goto err_ena; break; default: break; } dsp->booted = true; mutex_unlock(&dsp->pwr_lock); return; err_ena: regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); err_mem: regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_MEM_ENA, 0); err_mutex: mutex_unlock(&dsp->pwr_lock); } static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq) { int ret; switch (dsp->rev) { case 0: ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CLOCKING, ADSP2_CLK_SEL_MASK, freq << ADSP2_CLK_SEL_SHIFT); if (ret) { adsp_err(dsp, "Failed to set clock rate: %d\n", ret); return; } break; default: /* clock is handled by parent codec driver */ break; } } int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; struct wm_adsp *dsp = &dsps[mc->shift - 1]; ucontrol->value.integer.value[0] = dsp->preloaded; return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get); int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; struct wm_adsp *dsp = &dsps[mc->shift - 1]; char preload[32]; snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); dsp->preloaded = ucontrol->value.integer.value[0]; if (ucontrol->value.integer.value[0]) snd_soc_component_force_enable_pin(component, preload); else snd_soc_component_disable_pin(component, preload); snd_soc_dapm_sync(dapm); flush_work(&dsp->boot_work); return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put); static void wm_adsp_stop_watchdog(struct wm_adsp *dsp) { switch (dsp->rev) { case 0: case 1: return; default: regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG, ADSP2_WDT_ENA_MASK, 0); } } int wm_adsp2_early_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event, unsigned int freq) { struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); struct wm_adsp *dsp = &dsps[w->shift]; struct wm_coeff_ctl *ctl; switch (event) { case SND_SOC_DAPM_PRE_PMU: wm_adsp2_set_dspclk(dsp, freq); queue_work(system_unbound_wq, &dsp->boot_work); break; case SND_SOC_DAPM_PRE_PMD: mutex_lock(&dsp->pwr_lock); wm_adsp_debugfs_clear(dsp); dsp->fw_id = 0; dsp->fw_id_version = 0; dsp->booted = false; regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_MEM_ENA, 0); list_for_each_entry(ctl, &dsp->ctl_list, list) ctl->enabled = 0; wm_adsp_free_alg_regions(dsp); mutex_unlock(&dsp->pwr_lock); adsp_dbg(dsp, "Shutdown complete\n"); break; default: break; } return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_early_event); int wm_adsp2_event(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol, int event) { struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); struct wm_adsp *dsps = snd_soc_component_get_drvdata(component); struct wm_adsp *dsp = &dsps[w->shift]; int ret; switch (event) { case SND_SOC_DAPM_POST_PMU: flush_work(&dsp->boot_work); mutex_lock(&dsp->pwr_lock); if (!dsp->booted) { ret = -EIO; goto err; } ret = wm_adsp2_ena(dsp); if (ret != 0) goto err; /* Sync set controls */ ret = wm_coeff_sync_controls(dsp); if (ret != 0) goto err; wm_adsp2_lock(dsp, dsp->lock_regions); ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_CORE_ENA | ADSP2_START, ADSP2_CORE_ENA | ADSP2_START); if (ret != 0) goto err; if (wm_adsp_fw[dsp->fw].num_caps != 0) { ret = wm_adsp_buffer_init(dsp); if (ret < 0) goto err; } dsp->running = true; mutex_unlock(&dsp->pwr_lock); break; case SND_SOC_DAPM_PRE_PMD: /* Tell the firmware to cleanup */ wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN); wm_adsp_stop_watchdog(dsp); /* Log firmware state, it can be useful for analysis */ switch (dsp->rev) { case 0: wm_adsp2_show_fw_status(dsp); break; default: wm_adsp2v2_show_fw_status(dsp); break; } mutex_lock(&dsp->pwr_lock); dsp->running = false; regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_CORE_ENA | ADSP2_START, 0); /* Make sure DMAs are quiesced */ switch (dsp->rev) { case 0: regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0); regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA, 0); break; default: regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0); regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0); regmap_write(dsp->regmap, dsp->base + ADSP2V2_WDMA_CONFIG_2, 0); break; } if (wm_adsp_fw[dsp->fw].num_caps != 0) wm_adsp_buffer_free(dsp); dsp->fatal_error = false; mutex_unlock(&dsp->pwr_lock); adsp_dbg(dsp, "Execution stopped\n"); break; default: break; } return 0; err: regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0); mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp2_event); int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component) { char preload[32]; snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name); snd_soc_component_disable_pin(component, preload); wm_adsp2_init_debugfs(dsp, component); dsp->component = component; return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_component_probe); int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component) { wm_adsp2_cleanup_debugfs(dsp); return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_component_remove); int wm_adsp2_init(struct wm_adsp *dsp) { int ret; ret = wm_adsp_common_init(dsp); if (ret) return ret; switch (dsp->rev) { case 0: /* * Disable the DSP memory by default when in reset for a small * power saving. */ ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL, ADSP2_MEM_ENA, 0); if (ret) { adsp_err(dsp, "Failed to clear memory retention: %d\n", ret); return ret; } break; default: break; } INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work); return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_init); void wm_adsp2_remove(struct wm_adsp *dsp) { struct wm_coeff_ctl *ctl; while (!list_empty(&dsp->ctl_list)) { ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl, list); list_del(&ctl->list); wm_adsp_free_ctl_blk(ctl); } } EXPORT_SYMBOL_GPL(wm_adsp2_remove); static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr) { return compr->buf != NULL; } static int wm_adsp_compr_attach(struct wm_adsp_compr *compr) { struct wm_adsp_compr_buf *buf = NULL, *tmp; if (compr->dsp->fatal_error) return -EINVAL; list_for_each_entry(tmp, &compr->dsp->buffer_list, list) { if (!tmp->name || !strcmp(compr->name, tmp->name)) { buf = tmp; break; } } if (!buf) return -EINVAL; compr->buf = buf; compr->buf->compr = compr; return 0; } static void wm_adsp_compr_detach(struct wm_adsp_compr *compr) { if (!compr) return; /* Wake the poll so it can see buffer is no longer attached */ if (compr->stream) snd_compr_fragment_elapsed(compr->stream); if (wm_adsp_compr_attached(compr)) { compr->buf->compr = NULL; compr->buf = NULL; } } int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream) { struct wm_adsp_compr *compr, *tmp; struct snd_soc_pcm_runtime *rtd = stream->private_data; int ret = 0; mutex_lock(&dsp->pwr_lock); if (wm_adsp_fw[dsp->fw].num_caps == 0) { adsp_err(dsp, "%s: Firmware does not support compressed API\n", rtd->codec_dai->name); ret = -ENXIO; goto out; } if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) { adsp_err(dsp, "%s: Firmware does not support stream direction\n", rtd->codec_dai->name); ret = -EINVAL; goto out; } list_for_each_entry(tmp, &dsp->compr_list, list) { if (!strcmp(tmp->name, rtd->codec_dai->name)) { adsp_err(dsp, "%s: Only a single stream supported per dai\n", rtd->codec_dai->name); ret = -EBUSY; goto out; } } compr = kzalloc(sizeof(*compr), GFP_KERNEL); if (!compr) { ret = -ENOMEM; goto out; } compr->dsp = dsp; compr->stream = stream; compr->name = rtd->codec_dai->name; list_add_tail(&compr->list, &dsp->compr_list); stream->runtime->private_data = compr; out: mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp_compr_open); int wm_adsp_compr_free(struct snd_compr_stream *stream) { struct wm_adsp_compr *compr = stream->runtime->private_data; struct wm_adsp *dsp = compr->dsp; mutex_lock(&dsp->pwr_lock); wm_adsp_compr_detach(compr); list_del(&compr->list); kfree(compr->raw_buf); kfree(compr); mutex_unlock(&dsp->pwr_lock); return 0; } EXPORT_SYMBOL_GPL(wm_adsp_compr_free); static int wm_adsp_compr_check_params(struct snd_compr_stream *stream, struct snd_compr_params *params) { struct wm_adsp_compr *compr = stream->runtime->private_data; struct wm_adsp *dsp = compr->dsp; const struct wm_adsp_fw_caps *caps; const struct snd_codec_desc *desc; int i, j; if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE || params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE || params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS || params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS || params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) { compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n", params->buffer.fragment_size, params->buffer.fragments); return -EINVAL; } for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) { caps = &wm_adsp_fw[dsp->fw].caps[i]; desc = &caps->desc; if (caps->id != params->codec.id) continue; if (stream->direction == SND_COMPRESS_PLAYBACK) { if (desc->max_ch < params->codec.ch_out) continue; } else { if (desc->max_ch < params->codec.ch_in) continue; } if (!(desc->formats & (1 << params->codec.format))) continue; for (j = 0; j < desc->num_sample_rates; ++j) if (desc->sample_rates[j] == params->codec.sample_rate) return 0; } compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n", params->codec.id, params->codec.ch_in, params->codec.ch_out, params->codec.sample_rate, params->codec.format); return -EINVAL; } static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr) { return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE; } int wm_adsp_compr_set_params(struct snd_compr_stream *stream, struct snd_compr_params *params) { struct wm_adsp_compr *compr = stream->runtime->private_data; unsigned int size; int ret; ret = wm_adsp_compr_check_params(stream, params); if (ret) return ret; compr->size = params->buffer; compr_dbg(compr, "fragment_size=%d fragments=%d\n", compr->size.fragment_size, compr->size.fragments); size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf); compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL); if (!compr->raw_buf) return -ENOMEM; compr->sample_rate = params->codec.sample_rate; return 0; } EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params); int wm_adsp_compr_get_caps(struct snd_compr_stream *stream, struct snd_compr_caps *caps) { struct wm_adsp_compr *compr = stream->runtime->private_data; int fw = compr->dsp->fw; int i; if (wm_adsp_fw[fw].caps) { for (i = 0; i < wm_adsp_fw[fw].num_caps; i++) caps->codecs[i] = wm_adsp_fw[fw].caps[i].id; caps->num_codecs = i; caps->direction = wm_adsp_fw[fw].compr_direction; caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE; caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE; caps->min_fragments = WM_ADSP_MIN_FRAGMENTS; caps->max_fragments = WM_ADSP_MAX_FRAGMENTS; } return 0; } EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps); static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type, unsigned int mem_addr, unsigned int num_words, u32 *data) { struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); unsigned int i, reg; int ret; if (!mem) return -EINVAL; reg = wm_adsp_region_to_reg(mem, mem_addr); ret = regmap_raw_read(dsp->regmap, reg, data, sizeof(*data) * num_words); if (ret < 0) return ret; for (i = 0; i < num_words; ++i) data[i] = be32_to_cpu(data[i]) & 0x00ffffffu; return 0; } static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type, unsigned int mem_addr, u32 *data) { return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data); } static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type, unsigned int mem_addr, u32 data) { struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type); unsigned int reg; if (!mem) return -EINVAL; reg = wm_adsp_region_to_reg(mem, mem_addr); data = cpu_to_be32(data & 0x00ffffffu); return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data)); } static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf, unsigned int field_offset, u32 *data) { return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type, buf->host_buf_ptr + field_offset, data); } static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf, unsigned int field_offset, u32 data) { return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type, buf->host_buf_ptr + field_offset, data); } static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size) { u8 *pack_in = (u8 *)buf; u8 *pack_out = (u8 *)buf; int i, j; /* Remove the padding bytes from the data read from the DSP */ for (i = 0; i < nwords; i++) { for (j = 0; j < data_word_size; j++) *pack_out++ = *pack_in++; pack_in += sizeof(*buf) - data_word_size; } } static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf) { const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps; struct wm_adsp_buffer_region *region; u32 offset = 0; int i, ret; buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions), GFP_KERNEL); if (!buf->regions) return -ENOMEM; for (i = 0; i < caps->num_regions; ++i) { region = &buf->regions[i]; region->offset = offset; region->mem_type = caps->region_defs[i].mem_type; ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset, ®ion->base_addr); if (ret < 0) return ret; ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset, &offset); if (ret < 0) return ret; region->cumulative_size = offset; compr_dbg(buf, "region=%d type=%d base=%08x off=%08x size=%08x\n", i, region->mem_type, region->base_addr, region->offset, region->cumulative_size); } return 0; } static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf) { buf->irq_count = 0xFFFFFFFF; buf->read_index = -1; buf->avail = 0; } static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp) { struct wm_adsp_compr_buf *buf; buf = kzalloc(sizeof(*buf), GFP_KERNEL); if (!buf) return NULL; buf->dsp = dsp; wm_adsp_buffer_clear(buf); list_add_tail(&buf->list, &dsp->buffer_list); return buf; } static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp) { struct wm_adsp_alg_region *alg_region; struct wm_adsp_compr_buf *buf; u32 xmalg, addr, magic; int i, ret; buf = wm_adsp_buffer_alloc(dsp); if (!buf) return -ENOMEM; alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id); xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32); addr = alg_region->base + xmalg + ALG_XM_FIELD(magic); ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic); if (ret < 0) return ret; if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC) return -ENODEV; addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr); for (i = 0; i < 5; ++i) { ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &buf->host_buf_ptr); if (ret < 0) return ret; if (buf->host_buf_ptr) break; usleep_range(1000, 2000); } if (!buf->host_buf_ptr) return -EIO; buf->host_buf_mem_type = WMFW_ADSP2_XM; ret = wm_adsp_buffer_populate(buf); if (ret < 0) return ret; compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr); return 0; } static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl) { struct wm_adsp_host_buf_coeff_v1 coeff_v1; struct wm_adsp_compr_buf *buf; unsigned int val, reg; int ret, i; ret = wm_coeff_base_reg(ctl, ®); if (ret) return ret; for (i = 0; i < 5; ++i) { ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val)); if (ret < 0) return ret; if (val) break; usleep_range(1000, 2000); } if (!val) { adsp_err(ctl->dsp, "Failed to acquire host buffer\n"); return -EIO; } buf = wm_adsp_buffer_alloc(ctl->dsp); if (!buf) return -ENOMEM; buf->host_buf_mem_type = ctl->alg_region.type; buf->host_buf_ptr = be32_to_cpu(val); ret = wm_adsp_buffer_populate(buf); if (ret < 0) return ret; /* * v0 host_buffer coefficients didn't have versioning, so if the * control is one word, assume version 0. */ if (ctl->len == 4) { compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr); return 0; } ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1, sizeof(coeff_v1)); if (ret < 0) return ret; coeff_v1.versions = be32_to_cpu(coeff_v1.versions); val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK; val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT; if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) { adsp_err(ctl->dsp, "Host buffer coeff ver %u > supported version %u\n", val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER); return -EINVAL; } for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++) coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]); wm_adsp_remove_padding((u32 *)&coeff_v1.name, ARRAY_SIZE(coeff_v1.name), WM_ADSP_DATA_WORD_SIZE); buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part, (char *)&coeff_v1.name); compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n", buf->host_buf_ptr, val); return val; } static int wm_adsp_buffer_init(struct wm_adsp *dsp) { struct wm_coeff_ctl *ctl; int ret; list_for_each_entry(ctl, &dsp->ctl_list, list) { if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER) continue; if (!ctl->enabled) continue; ret = wm_adsp_buffer_parse_coeff(ctl); if (ret < 0) { adsp_err(dsp, "Failed to parse coeff: %d\n", ret); goto error; } else if (ret == 0) { /* Only one buffer supported for version 0 */ return 0; } } if (list_empty(&dsp->buffer_list)) { /* Fall back to legacy support */ ret = wm_adsp_buffer_parse_legacy(dsp); if (ret) { adsp_err(dsp, "Failed to parse legacy: %d\n", ret); goto error; } } return 0; error: wm_adsp_buffer_free(dsp); return ret; } static int wm_adsp_buffer_free(struct wm_adsp *dsp) { struct wm_adsp_compr_buf *buf, *tmp; list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) { if (buf->compr) wm_adsp_compr_detach(buf->compr); kfree(buf->name); kfree(buf->regions); list_del(&buf->list); kfree(buf); } return 0; } static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf) { int ret; ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error); if (ret < 0) { compr_err(buf, "Failed to check buffer error: %d\n", ret); return ret; } if (buf->error != 0) { compr_err(buf, "Buffer error occurred: %d\n", buf->error); return -EIO; } return 0; } int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd) { struct wm_adsp_compr *compr = stream->runtime->private_data; struct wm_adsp *dsp = compr->dsp; int ret = 0; compr_dbg(compr, "Trigger: %d\n", cmd); mutex_lock(&dsp->pwr_lock); switch (cmd) { case SNDRV_PCM_TRIGGER_START: if (!wm_adsp_compr_attached(compr)) { ret = wm_adsp_compr_attach(compr); if (ret < 0) { compr_err(compr, "Failed to link buffer and stream: %d\n", ret); break; } } ret = wm_adsp_buffer_get_error(compr->buf); if (ret < 0) break; /* Trigger the IRQ at one fragment of data */ ret = wm_adsp_buffer_write(compr->buf, HOST_BUFFER_FIELD(high_water_mark), wm_adsp_compr_frag_words(compr)); if (ret < 0) { compr_err(compr, "Failed to set high water mark: %d\n", ret); break; } break; case SNDRV_PCM_TRIGGER_STOP: if (wm_adsp_compr_attached(compr)) wm_adsp_buffer_clear(compr->buf); break; default: ret = -EINVAL; break; } mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger); static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf) { int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1; return buf->regions[last_region].cumulative_size; } static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf) { u32 next_read_index, next_write_index; int write_index, read_index, avail; int ret; /* Only sync read index if we haven't already read a valid index */ if (buf->read_index < 0) { ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_read_index), &next_read_index); if (ret < 0) return ret; read_index = sign_extend32(next_read_index, 23); if (read_index < 0) { compr_dbg(buf, "Avail check on unstarted stream\n"); return 0; } buf->read_index = read_index; } ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index), &next_write_index); if (ret < 0) return ret; write_index = sign_extend32(next_write_index, 23); avail = write_index - buf->read_index; if (avail < 0) avail += wm_adsp_buffer_size(buf); compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n", buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE); buf->avail = avail; return 0; } int wm_adsp_compr_handle_irq(struct wm_adsp *dsp) { struct wm_adsp_compr_buf *buf; struct wm_adsp_compr *compr; int ret = 0; mutex_lock(&dsp->pwr_lock); if (list_empty(&dsp->buffer_list)) { ret = -ENODEV; goto out; } adsp_dbg(dsp, "Handling buffer IRQ\n"); list_for_each_entry(buf, &dsp->buffer_list, list) { compr = buf->compr; ret = wm_adsp_buffer_get_error(buf); if (ret < 0) goto out_notify; /* Wake poll to report error */ ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count), &buf->irq_count); if (ret < 0) { compr_err(buf, "Failed to get irq_count: %d\n", ret); goto out; } ret = wm_adsp_buffer_update_avail(buf); if (ret < 0) { compr_err(buf, "Error reading avail: %d\n", ret); goto out; } if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2) ret = WM_ADSP_COMPR_VOICE_TRIGGER; out_notify: if (compr && compr->stream) snd_compr_fragment_elapsed(compr->stream); } out: mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq); static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf) { if (buf->irq_count & 0x01) return 0; compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count); buf->irq_count |= 0x01; return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack), buf->irq_count); } int wm_adsp_compr_pointer(struct snd_compr_stream *stream, struct snd_compr_tstamp *tstamp) { struct wm_adsp_compr *compr = stream->runtime->private_data; struct wm_adsp *dsp = compr->dsp; struct wm_adsp_compr_buf *buf; int ret = 0; compr_dbg(compr, "Pointer request\n"); mutex_lock(&dsp->pwr_lock); buf = compr->buf; if (!compr->buf || compr->buf->error) { snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); ret = -EIO; goto out; } if (buf->avail < wm_adsp_compr_frag_words(compr)) { ret = wm_adsp_buffer_update_avail(buf); if (ret < 0) { compr_err(compr, "Error reading avail: %d\n", ret); goto out; } /* * If we really have less than 1 fragment available tell the * DSP to inform us once a whole fragment is available. */ if (buf->avail < wm_adsp_compr_frag_words(compr)) { ret = wm_adsp_buffer_get_error(buf); if (ret < 0) { if (compr->buf->error) snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN); goto out; } ret = wm_adsp_buffer_reenable_irq(buf); if (ret < 0) { compr_err(compr, "Failed to re-enable buffer IRQ: %d\n", ret); goto out; } } } tstamp->copied_total = compr->copied_total; tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE; tstamp->sampling_rate = compr->sample_rate; out: mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer); static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target) { struct wm_adsp_compr_buf *buf = compr->buf; unsigned int adsp_addr; int mem_type, nwords, max_read; int i, ret; /* Calculate read parameters */ for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i) if (buf->read_index < buf->regions[i].cumulative_size) break; if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions) return -EINVAL; mem_type = buf->regions[i].mem_type; adsp_addr = buf->regions[i].base_addr + (buf->read_index - buf->regions[i].offset); max_read = wm_adsp_compr_frag_words(compr); nwords = buf->regions[i].cumulative_size - buf->read_index; if (nwords > target) nwords = target; if (nwords > buf->avail) nwords = buf->avail; if (nwords > max_read) nwords = max_read; if (!nwords) return 0; /* Read data from DSP */ ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr, nwords, compr->raw_buf); if (ret < 0) return ret; wm_adsp_remove_padding(compr->raw_buf, nwords, WM_ADSP_DATA_WORD_SIZE); /* update read index to account for words read */ buf->read_index += nwords; if (buf->read_index == wm_adsp_buffer_size(buf)) buf->read_index = 0; ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index), buf->read_index); if (ret < 0) return ret; /* update avail to account for words read */ buf->avail -= nwords; return nwords; } static int wm_adsp_compr_read(struct wm_adsp_compr *compr, char __user *buf, size_t count) { int ntotal = 0; int nwords, nbytes; compr_dbg(compr, "Requested read of %zu bytes\n", count); if (!compr->buf || compr->buf->error) { snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); return -EIO; } count /= WM_ADSP_DATA_WORD_SIZE; do { nwords = wm_adsp_buffer_capture_block(compr, count); if (nwords < 0) { compr_err(compr, "Failed to capture block: %d\n", nwords); return nwords; } nbytes = nwords * WM_ADSP_DATA_WORD_SIZE; compr_dbg(compr, "Read %d bytes\n", nbytes); if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) { compr_err(compr, "Failed to copy data to user: %d, %d\n", ntotal, nbytes); return -EFAULT; } count -= nwords; ntotal += nbytes; } while (nwords > 0 && count > 0); compr->copied_total += ntotal; return ntotal; } int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf, size_t count) { struct wm_adsp_compr *compr = stream->runtime->private_data; struct wm_adsp *dsp = compr->dsp; int ret; mutex_lock(&dsp->pwr_lock); if (stream->direction == SND_COMPRESS_CAPTURE) ret = wm_adsp_compr_read(compr, buf, count); else ret = -ENOTSUPP; mutex_unlock(&dsp->pwr_lock); return ret; } EXPORT_SYMBOL_GPL(wm_adsp_compr_copy); int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions) { struct regmap *regmap = dsp->regmap; unsigned int code0, code1, lock_reg; if (!(lock_regions & WM_ADSP2_REGION_ALL)) return 0; lock_regions &= WM_ADSP2_REGION_ALL; lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0; while (lock_regions) { code0 = code1 = 0; if (lock_regions & BIT(0)) { code0 = ADSP2_LOCK_CODE_0; code1 = ADSP2_LOCK_CODE_1; } if (lock_regions & BIT(1)) { code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT; code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT; } regmap_write(regmap, lock_reg, code0); regmap_write(regmap, lock_reg, code1); lock_regions >>= 2; lock_reg += 2; } return 0; } EXPORT_SYMBOL_GPL(wm_adsp2_lock); static void wm_adsp_fatal_error(struct wm_adsp *dsp) { struct wm_adsp_compr *compr; dsp->fatal_error = true; list_for_each_entry(compr, &dsp->compr_list, list) { if (compr->stream) { snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN); snd_compr_fragment_elapsed(compr->stream); } } } irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp) { unsigned int val; struct regmap *regmap = dsp->regmap; int ret = 0; mutex_lock(&dsp->pwr_lock); ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val); if (ret) { adsp_err(dsp, "Failed to read Region Lock Ctrl register: %d\n", ret); goto error; } if (val & ADSP2_WDT_TIMEOUT_STS_MASK) { adsp_err(dsp, "watchdog timeout error\n"); wm_adsp_stop_watchdog(dsp); wm_adsp_fatal_error(dsp); } if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) { if (val & ADSP2_SLAVE_ERR_MASK) adsp_err(dsp, "bus error: slave error\n"); else adsp_err(dsp, "bus error: region lock error\n"); ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val); if (ret) { adsp_err(dsp, "Failed to read Bus Err Addr register: %d\n", ret); goto error; } adsp_err(dsp, "bus error address = 0x%x\n", val & ADSP2_BUS_ERR_ADDR_MASK); ret = regmap_read(regmap, dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR, &val); if (ret) { adsp_err(dsp, "Failed to read Pmem Xmem Err Addr register: %d\n", ret); goto error; } adsp_err(dsp, "xmem error address = 0x%x\n", val & ADSP2_XMEM_ERR_ADDR_MASK); adsp_err(dsp, "pmem error address = 0x%x\n", (val & ADSP2_PMEM_ERR_ADDR_MASK) >> ADSP2_PMEM_ERR_ADDR_SHIFT); } regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT); error: mutex_unlock(&dsp->pwr_lock); return IRQ_HANDLED; } EXPORT_SYMBOL_GPL(wm_adsp2_bus_error); MODULE_LICENSE("GPL v2");рабочий пример для кодеков Wolfson под ADSP
-
вот пример для распространенного ЦАП CS4385A:
Spoiler#include "./include/cs4385a.h"
#include <def21489.h>
#include <cdef21489.h>
#include <math.h>
#include "./include/ADDS_21489_EzKit.h"
#include <sru.h>
#include <sysreg.h>
#include <stdio.h>#if 0
#define SHIFT_NUMBER 31#define NOP asm volatile("nop;")
//
/*
*
* ¶аНЁµА(TDM)РиТЄЕдЦГµДјДґжЖч
*
* DIVx
* SPCTLx
* SPCTLNx
* SPMCTLx
* MTxCSy,MRxCSy
* MTxCCSy,MRxCCSy
* SPERRCTLx
* SPERRSTAT
*
* see reference at : ADSP-214xx SHARC Processor Hardware Reference,Rev. 0.3 . P515.
*
*
* P1148 as the TDM MODE detail.
*
* К№УГSPCTLxєНSPMCTLxЕдЦГSPORTФЛРРФЪ¶аНЁµАДЈКЅЎЈ
*///section("seg_ext_dmda")
int TxBlock_TDM_CS4385[2][CIRCLEDAMDATABUFFNUM*NUM_SAMPLES*NUM_TX_SLOTS * 8/2];
int TCB_TxBlock_TDM_CS4385[2][CIRCLEDAMDATABUFFNUM][4];static unsigned int PCI = 0x00080000;
static unsigned int OFFSET = 0x00080000;
void clearDAIpins()
{
//------------------------------------------------------------------------
// Tie the pin buffer inputs LOW for all DAI pins. Even though
// these pins are inputs to the SHARC, tying unused pin buffer inputs
// LOW is "good coding style" to eliminate the possibility of
// termination artifacts internal to the IC. Note that signal
// integrity is degraded only with a few specific SRU combinations.
// In practice, this occurs VERY rarely, and these connections are
// typically unnecessary. This is GROUP D
SRU(LOW, DAI_PB01_I);
SRU(LOW, DAI_PB02_I);
SRU(LOW, DAI_PB03_I);
SRU(LOW, DAI_PB04_I);
SRU(LOW, DAI_PB05_I);
SRU(LOW, DAI_PB06_I);
SRU(LOW, DAI_PB07_I);
SRU(LOW, DAI_PB08_I);
SRU(LOW, DAI_PB09_I);
SRU(LOW, DAI_PB10_I);
SRU(LOW, DAI_PB11_I);
SRU(LOW, DAI_PB12_I);
SRU(LOW, DAI_PB13_I);
SRU(LOW, DAI_PB14_I);
SRU(LOW, DAI_PB15_I);
SRU(LOW, DAI_PB16_I);
SRU(LOW, DAI_PB17_I);
SRU(LOW, DAI_PB18_I);
SRU(LOW, DAI_PB19_I);
SRU(LOW, DAI_PB20_I);//------------------------------------------------------------------------
// Tie the pin buffer enable inputs LOW for all DAI pins so
// that they are always input pins. This is GROUP F.
SRU(LOW, PBEN01_I);
SRU(LOW, PBEN02_I);
SRU(LOW, PBEN03_I);
SRU(LOW, PBEN04_I);
SRU(LOW, PBEN05_I);
SRU(LOW, PBEN06_I);
SRU(LOW, PBEN07_I);
SRU(LOW, PBEN08_I);
SRU(LOW, PBEN09_I);
SRU(LOW, PBEN10_I);
SRU(LOW, PBEN11_I);
SRU(LOW, PBEN12_I);
SRU(LOW, PBEN13_I);
SRU(LOW, PBEN14_I);
SRU(LOW, PBEN15_I);
SRU(LOW, PBEN16_I);
SRU(LOW, PBEN17_I);
SRU(LOW, PBEN18_I);
SRU(LOW, PBEN19_I);
SRU(LOW, PBEN20_I);
}
/*
*
* 2016-10-08 by yuan at qj
*
* DAРѕЖ¬µДіхКј»ЇµИ
*
* DAI_P07 TDM_DA_BCLK1
* DAI_P19 TDM_DA_LRCLK1
* DAI_P13 TDM_DA_DATA01
* DAI_P01 TDM_DA_DATA02
*
* К№УГTDMµДЕдЦГ·ЅКЅ
*/
void CS4385A_Pin_Init(void)
{
SRU(HIGH,PBEN07_I);
SRU(PCG_CLKB_O, DAI_PB07_I);
SRU(PCG_CLKB_O, SPORT0_CLK_I);//DA-LRCLK----DAI.19
SRU(HIGH,PBEN19_I);
SRU(PCG_FSB_O, SPORT0_FS_I);
SRU(PCG_FSB_O, DAI_PB19_I);//DA-DATA01-----DAI.01
SRU(HIGH,PBEN01_I);
SRU(SPORT0_DB_O,DAI_PB01_I);
//DA-DATA02-----DAI.13
SRU(HIGH,PBEN13_I);
SRU(SPORT0_DA_O,DAI_PB13_I);
}void CS4385A_Reset(void)
{
int i;
//****************************reset DA**************************
SRU(HIGH, DPI_PBEN06_I);
SRU(LOW, DPI_PB06_I); //DA_RESET
for(i = 0; i < 65536 ; i++)
NOP;SRU(HIGH, DPI_PB06_I); //DA_RESET
//Wait for recommended number of cycles
for(i = 0; i < 4096; i++)
NOP;
}/*
*
* DA_Mute№ЬЅЕ : DPI_P08
*
*
*/
void CS4385A_Mute(int i_choice)
{
int i;//****************************reset DA**************************
SRU(HIGH, DPI_PBEN08_I);
switch(i_choice)
{
case 0://unmute
SRU(LOW, DPI_PB08_I);
break;
case 1://mute
SRU(HIGH, DPI_PB08_I);
break;
}
for(i = 0; i < 4096; i++)
NOP;
}
static void Init_PCG(void )
{
int i = 0;
static int Init_PCG_FLAG = 0;
if(Init_PCG_FLAG == 1)
return ;Init_PCG_FLAG = 1;
//PCGµДК±ЦУКдИл
SRU(LOW,PBEN03_I); //PCG DAI_P03 ЈЁPCK clk inputЈ©
SRU(DAI_PB03_O,PCG_EXTB_I); //PCG clock in
*pPCG_CTLB1 = (2) | CLKBSOURCE | FSBSOURCE | ((2/2)<<20); //Division for clock
*pPCG_CTLB0 = 512 | ENCLKB | ENFSB; // Frame syn Division
*pPCG_PW = (2 << 16);
}
void CS4385A_InitData(void)
{
int i = 0;
int j = 0;
//Setting Up and Starting Chained DMA
//1.Clear the chain pointer register.
*pCPSP0A = 0;
//Д¬ИПґ¦Ан
//as the reference say
//1.Clear all control registers
*pSPCTL0 = 0;
*pSPMCTL0 = 0;
*pSP0CS0 = 0;
*pSP1CS0 = 0;
//2.configure the channel section register
*pSP0CS0 = 0xff;//TX//8НЁµА
*pSP1CS0 = 0; //RX
*pMT0CCS0 = 0;
//*pMT0CS0 = 0xff;
//*pDIV0 = 0x008F0002;//ЧчОЄДЪІїК±ЦУ·ЦЖµК№УГ
//3.configure the dma parameter registers.index,modify,count etc..
//printf("---use tdm configuration----\n");
for(i = 0 ; i < 2 ; i ++)
{
for(j = 0; j < CIRCLEDMADATABUFFNUM; j++){
TCB_TxBlock_TDM_CS4385[j][0] = (unsigned int)(TCB_TxBlock_TDM_CS4385[( j + 1 ) % CIRCLEDMADATABUFFNUM]) + 3 - OFFSET + PCI ;
TCB_TxBlock_TDM_CS4385[j][1] = NUM_SAMPLES * NUM_TX_SLOTS * 8/2;
TCB_TxBlock_TDM_CS4385[j][2] = 1;
TCB_TxBlock_TDM_CS4385[j][3] = (int)(&TxBlock_TDM_CS4385[j * NUM_SAMPLES * NUM_TX_SLOTS * 8 /2 ]);
}
}
//3.Write the address containing the index register value of the first TCB to the chain pointer register, which starts the chain.
*pCPSP0A = (unsigned int)(TCB_TxBlock_TDM_CS4385[0][0]) - OFFSET + 3 + PCI;
*pCPSP0B = (unsigned int)(TCB_TxBlock_TDM_CS4385[1][0]) - OFFSET + 3 + PCI;
//4.configure the sport control register ,SPCTLx and enable the dma chaining.
//printf("-----use tdm configuration-----------\n");
//reference P482.Multichannel Mode
*pSPCTL0 = (
SPTRAN //SPTRAN=1 transfer
//| OPMODE //I2S mode
| SLEN32 //word length = 32
// | SPEN_A //serial port A channel enable
| SCHEN_A //Enable serial port channal A DMA channing
| SDEN_A //Enable serial port channal A DMA
| L_FIRST //Left channal first
//| CKRE //ЙПЙэСШІЙСщ
//| DIFS
//| BHD
| SCHEN_B //Enable serial port channal B DMA channing
| SDEN_B //Enable serial port channal B DMA
);
//5.configure the receiver SPORT pair SPCTLy and enable the dma chaining.
//6.in multiple mode, operation starts as soon as the MCEx bit is enabled.
//7.configure and enable multichannel in the multichannel control registers.
*pSPCTLN0 |= FSED;
while(1)
{
if((*pSPCTL0 & (DXS0_A | DXS0_B)))
break;
}
*pSPMCTL0 = (NCH7);
*pSPMCTL0 |= MCEA;
for(i = 0; i < 10000; i++)
NOP;
}void Clear_CS4385_Buffer(void)
{
memset(TxBlock_TDM_CS4385[0],0,CIRCLEDAMDATABUFFNUM*NUM_SAMPLES*NUM_TX_SLOTS * 8/2 * sizeof(int));
memset(TxBlock_TDM_CS4385[1],0,CIRCLEDAMDATABUFFNUM*NUM_SAMPLES*NUM_TX_SLOTS * 8/2 * sizeof(int));
}
void Stop_CS4385_DMA(){*pCPSP0A = 0;
*pCPSP0B = 0;
}void dai_isr(int sig){
int temp;
temp = *pDAI_IRPTL_H;
}section("seg_ext_dmda") int g_temp[NUM_SAMPLES * NUM_TX_SLOTS * CIRCLEDMADATABUFFNUM];
void ReadFile( void )
{
FILE* file_p;
int i;
// return;
// printf("write file\n");
// return;
//printf("\n");
file_p = fopen("../a.wav","rb");
if(file_p == NULL)
{
printf("file open bad\n");
}
else
{
printf("file open ok\n");
}
printf("----------read file start------");//РґОДјю
fread(g_temp,1,NUM_SAMPLES * NUM_TX_SLOTS * CIRCLEDMADATABUFFNUM ,file_p);
//fwrite(DIR9001_RxBlock_TDM_Temp,1,NUM_SAMPLES *NUM_RX_SLOTS,file_p);for(i = 0 ; i < NUM_SAMPLES * NUM_TX_SLOTS * CIRCLEDMADATABUFFNUM ;i ++)
{
TxBlock_TDM_CS4385[0][8*i+0] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+1] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+2] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+3] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+4] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+5] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+6] = g_temp << 15 ;
TxBlock_TDM_CS4385[0][8*i+7] = g_temp << 15 ;
}
fclose(file_p);
printf("----------read file end-------\n");
}
#define DA_DIVIDER_VALUE (1)void WaveFun2()
{
int i = 0;
int g_sinBaseValue = 100;
// ReadFile();
}
int Get_Current_CS4385_Dma_Txblock(){int i;
for (i = 0; i < 4; i++){
if (*pCPSP0A == (unsigned int)(TCB_TxBlock_TDM_CS4385[0]) - OFFSET + 3 + PCI)
break;
}
return (i < 4) ? i : 0;
}void Register_DA_Interrupt( void )
{
interrupt(SIG_SP0, SP0ADCSend_ISR);
}
void Re_Init_CS4385()
{
Stop_CS4385_DMA();
CS4385A_InitData();
//їЄЖф
//CS4385A_Mute(0);
//ЧўІбDAЦР¶П
Register_DA_Interrupt();
}
/*
*
*
* CS4385AіхКј»Ї
*
* ОЄ¶ФНвЅУїЪ
*
*/
void CS4385A_Init(void)
{
//PCGіхКј»Ї
Init_PCG();
//ТэЅЕіхКј»Ї
CS4385A_Pin_Init( );
//CS4385AіхКј»Ї
CS4385A_Reset();
CS4385A_InitData();
//їЄЖф
//CS4385A_Mute(0);
//ЧўІбDAЦР¶П
Register_DA_Interrupt();
}#endif
-
On 4/2/2019 at 3:51 PM, izolenta said:
Тогда почему нигде в даташите или рефмане об этом не сказано и не указано?
А вы возьмите реальные камни и проверьте эту "инсайдерскую" информацию
-
в ST для хранения калибровочных данных используются разные адреса в зависимости от чипа
Chip CAL1 CAL2 L15+[CRUV]C 0x1FF800FA 0x1FF800FE L162[RV]C 0x1FF800FA 0x1FF800FE L15[12]+[68B] 0x1FF8007A 0x1FF8007E -
я часто бываю рассеянным
А ваше замечание учту.
-
есть пример по PDM в верилог
`timescale 1ns / 1ps module Mic_Demo( output anout, output ampSD, output sclk, output ncs, input sdata, input clk ); reg [4:0]clk_cntr_reg; reg pwm_val_reg; always @(posedge clk) begin clk_cntr_reg <= clk_cntr_reg + 1; end always @(posedge clk) begin if(clk_cntr_reg == 5'b01111) begin pwm_val_reg <= sdata; end end //sclk = 100MHz / 32 = 3.125 MHz assign sclk = clk_cntr_reg[4]; assign anout = pwm_val_reg; assign ncs = 1'b0; //mic LRSel assign ampSD = 1'b1; endmodule -
Набивание постов?
7 hours ago, Vasily_ said:Это вы в прошлое?
Набивание постов?
для чего?
-
Матлаб не поддерживает целочисленные матрицы при произведении
Попробуй так:multiplied = double(singleMat) * double(singleMatT);или
multiplied = single(singleMat) * single(singleMatT); -
-
-
Уже не работает!
-
- // чтение из регистра W5300
- uint16_t ReadReg (uint16_t Addr)
- {
- uint16_t data;
- GPIOD->MODER = 0x00000000; // порт для данных сделать входом
- GPIOE->ODR = Addr;
- GPIOB->ODR = 0x00009800; // WRC
- data = GPIOD->IDR;
- GPIOB->ODR = 0x0000F800; // WRC
- GPIOE->ODR = Addr;
- GPIOD->MODER = 0x55555555; // порт D сделать выходом
- return (data);
- }
- // запись в регистр W5300
- void WriteReg (uint16_t Addr, uint16_t Data)
- {
- GPIOE->ODR = Addr;
- GPIOD->ODR = Data;
- GPIOB->ODR = 0x00005800; // WRC
- __NOP();
- GPIOB->ODR = 0x0000F800; // WRC
- GPIOE->ODR = 0x0000;
- GPIOD->ODR = 0x0000;
- }
Тут я думаю, ничего сложного.
STM32407 IAR 8.50.6 разместить байты по адресу во FLASH
в ARM, 32bit
Опубликовано · Пожаловаться
Можно использовать данную функцию для записи во flash с помощью HAL библиотеки: