[wator 0]

Когда-то давно использовалась такая функция:

int PLL_Init()
{
   CSL_Status               status_pllc1;
   CSL_PllcHwSetup          hwSetup_pllc1;
   CSL_PllcHwSetup          hwSetupRead_pllc1;    

   // Initialize the PLLC CSL module 
   status_pllc1 = CSL_pllcInit(0);
   if(status_pllc1 != CSL_SOK) return 1;


   // Clear local data structures 
   memset(&pllc1, 0, sizeof(CSL_PllcObj));

   // Open the PLLC CSL module 
   hPll1 = CSL_pllcOpen(&pllc1, CSL_PLLC_1, 0, &status_pllc1);
   if((hPll1 == 0) || (status_pllc1 != CSL_SOK))  return 2;


   // Setup PLLC hardware parameters 
   hwSetup_pllc1.divEnable  = (CSL_BitMask32) CSL_PLLC_DIVEN_PLLDIV4 | CSL_PLLC_DIVEN_PREDIV |
                           CSL_PLLC_DIVEN_PLLDIV5;

   hwSetup_pllc1.preDiv = 1;
   hwSetup_pllc1.pllM = 20;
   hwSetup_pllc1.pllDiv4 = 2;    

   hwSetup_pllc1.pllDiv5 = (Uint32)0x00000002;
hwSetup_pllc1.pllMode = CSL_PLLC_PLLCTL_PLLEN_PLL;

   status_pllc1 = CSL_pllcHwSetup(hPll1, &hwSetup_pllc1);
   if(status_pllc1 != CSL_SOK) 
   {
	status_pllc1 = CSL_pllcClose(hPll1);
   	return 3;
}

   // Read back 
   status_pllc1 = CSL_pllcGetHwSetup(hPll1, &hwSetupRead_pllc1);
   if(status_pllc1 != CSL_SOK) 
   {
	status_pllc1 = CSL_pllcClose(hPll1);
   	return 4;
}

// PLL2 Settings

CSL_Status               status_pllc2;
   CSL_PllcHwSetup          hwSetup_pllc2;
   CSL_PllcDivideControl    arg1_pllc2;
   CSL_PllcDivRatio         arg2_pllc2;
   CSL_BitMask32            response_pllc2;   
   CSL_BitMask32            argPllCtrl; 

 // Clear local data structures 
   memset(&pllc2, 0, sizeof(CSL_PllcObj));

   // Open the PLLC CSL module 
   hPll2 = CSL_pllcOpen(&pllc2, CSL_PLLC_2, 0, &status_pllc2);

// Setup PLLC hardware parameters 
   hwSetup_pllc2.divEnable  = 0;
hwSetup_pllc2.pllDiv1 = 5;
hwSetup_pllc2.pllMode = CSL_PLLC_PLLCTL_PLLEN_PLL;

   CSL_pllcHwSetup(hPll2, &hwSetup_pllc2);

// Command to enable PLLDIV4 
   arg1_pllc2.divNum = CSL_PLLC_DIVSEL_PLLDIV1;
   arg1_pllc2.divCtrl = CSL_PLLC_PLLDIV_ENABLE;
CSL_pllcHwControl(hPll2, CSL_PLLC_CMD_PLLDIV_CONTROL, &arg1_pllc2);

   // Command to change PLLDIV1 Divider Ratio 
   arg2_pllc2.divNum = CSL_PLLC_DIVSEL_PLLDIV1;    
   arg2_pllc2.divRatio = 5;
   CSL_pllcHwControl(hPll2, CSL_PLLC_CMD_SET_PLLRATIO, &arg2_pllc2);

   // Set GOSET bit to change/set the dividers 
   argPllCtrl = 0x010000;   // value to set the GOSET bit  
   CSL_pllcHwControl(hPll2, CSL_PLLC_CMD_PLLCONTROL, &argPllCtrl);

   // Poll for divide-ratio change and clock alignment to complete 
   do {
       CSL_pllcGetHwStatus (hPll2, CSL_PLLC_QUERY_STATUS, &response_pllc2);
   } while (response_pllc2 & CSL_PLLC_STATUS_GO);


return 0;
}

Правильность установки частоты проверялась на ноге GP1/SYSCLK4.

Огромное спасибо! Все работает. Выручили.