ClockworkOrange 0 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба при имплементации проекта на этапе временного анализа в командном окне выводится: >> Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) >> Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) >> Device speed data version: "PRODUCTION 1.26 2006-08-18". как можно изменить значения, по умолчанию заданные в этом анализе?... .т.е. например температуру +40С (если наверняка известно, что прибор будет работать в диапазоне от +15 до максимум +35С). полазил по закладкам МАР и PAR - не нашел такого.. а ведь где-то задаётся (и наверняка меняется!!!) цель: не укладываюсь в производительность. С учётом ышеприведенных условий хотелось бы более точной оценки + иметь возможность проводить временное моделирование на реальной частоте. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
vetal 0 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба Оверклокингом занимаетесь? Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
ClockworkOrange 0 22 мая, 2007 Опубликовано 22 мая, 2007 (изменено) · Жалоба откровенно говоря не понимаю иронии. обращаю ваше внимание на то ,что у производителя для каждого кристалла есть несколько версий: для стандартного диапазона температур ( C ) и для расширенного (I), для стандартного быстродействия (условно) и повышенного, притом идентичность цен на C-fast и I-slow подталкивает к выводу, что в ассортименте не три варианта (C-fast, С-slow и I-slow), а два: C-fast и С-slow. т.е. для раширения диапазона рабочих температур необходимо маркировать меньшим быстродействием ( ну может еще и этап корпусирования чипов отличен) - так это означает и обратное: при сужении вилки температур эксплуатации гарантирована работа при бОльших частотах тактирования. Так что всё "законно" - я просто хочу оценить задержку официальным софтом с иными нач.условиями Изменено 22 мая, 2007 пользователем ClockworkOrange Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
makc 207 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба Читайте Constraints Guide в Software Manuals на тему констрейнов TEMPERАTURE и VOLTAGE. TEMPERATURE Applicable Elements Global TEMPERATURE Description TEMPERATURE is an advanced timing constraint. It allows the specification of the operating junction temperature. TEMPERATURE provides a means of device delay characteristics based on the specified temperature. Prorating is a scaling operation on existing speed file delays and is applied globally to all delays. Note: Newer devices may not support Temperature prorating until the timing information (speed files) are marked as production status. Each architecture has its own specific range of valid operating temperatures. If the entered temperature does not fall within the supported range, TEMPERATURE is ignored and an architecture-specific worst-case value is used instead. Also note that the error message for this condition does not appear until static timing. VOLTAGE Applicable Elements Global VOLTAGE Description VOLTAGE is an advanced timing constraint. It allows the specification of the operating voltage, which provides a means of prorating delay characteristics based on the specified voltage. Prorating is a scaling operation on existing speed file delays and is applied globally to all delays. Note: Newer devices may not support Voltage prorating until the timing information (speed files) are marked as production status. Each architecture has its own specific range of supported voltages. If the entered voltage does not fall within the supported range, the constraint is ignored and an architecturespecific default value is used instead. Also note that the error message for this condition appears during static timing. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
ClockworkOrange 0 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба >> Initializing temperature to 25.000 Celsius. (derated - Range: -40.000 to 100.000 Celsius) >> Initializing voltage to 1.200 Volts. (derated - Range: 1.140 to 1.320 Volts) >> Device speed data version: "PRODUCTION 1.26 2006-08-18". но результат оценки таймингов после PAR'a прежний (((( может надо не только в UCF, но и в неком PCF прописывать констрэйны? или во всём виноват жёсткий "Range: -40.000 to 100.000 Celsius" ?? Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
makc 207 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба >> Initializing temperature to 25.000 Celsius. (derated - Range: -40.000 to 100.000 Celsius) >> Initializing voltage to 1.200 Volts. (derated - Range: 1.140 to 1.320 Volts) >> Device speed data version: "PRODUCTION 1.26 2006-08-18". но результат оценки таймингов после PAR'a прежний (((( может надо не только в UCF, но и в неком PCF прописывать констрэйны? или во всём виноват жёсткий "Range: -40.000 to 100.000 Celsius" ?? Может быть дело не только в пресловутой температуте и напряжении питания? Вы бы привели свой Timing report, в котором написано, какие констрейны и почему не выполняются. Тогда ситуация станет намного понятнее. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
ClockworkOrange 0 22 мая, 2007 Опубликовано 22 мая, 2007 (изменено) · Жалоба File: embedded_kcpsm3_last_par.dly Release 8.2.03i - reportgen I.34 Copyright © 1995-2006 Xilinx, Inc. All rights reserved. Tue May 22 21:12:55 2007 File: embedded_kcpsm3_last_par.dly The 20 worst nets by delay are: +-----------------+-----------+ | Max Delay | Netname | +-----------------+-----------+ 3.208 processor/t_state 3.003 processor/stack_address<1> 2.933 processor/internal_reset 2.873 instruction<15> 2.853 port_id_3_OBUF 2.748 processor/active_interrupt 2.739 port_id_4_OBUF 2.617 processor/stack_address<2> 2.493 in_port_7_IBUF 2.425 processor/stack_address<0> 2.354 processor/clean_int 2.326 instruction<16> 2.304 processor/stack_pop_data<4> 2.303 port_id_5_OBUF 2.256 processor/stack_address<3> 2.254 instruction<17> 2.240 processor/stack_address<4> 2.200 address<4> 2.190 processor/stack_pop_data<2> 2.182 in_port_6_IBUF --------------------------------- ------------------------------------------------------------------------------- Net Delays ------------------------------------------------------------------------------- address<0> address<0>.XQ 1.224 prog_rom/ram_1024_x_18.ADDRA4 0.820 address<0>.F1 1.622 processor/stack_pop_data<0>.BY address<1> address<0>.YQ 1.636 prog_rom/ram_1024_x_18.ADDRA5 1.308 address<0>.G1 2.026 processor/stack_pop_data<1>.BY address<2> address<2>.XQ 1.799 prog_rom/ram_1024_x_18.ADDRA6 0.512 address<2>.F1 1.856 processor/stack_pop_data<2>.BY address<3> address<2>.YQ 1.520 prog_rom/ram_1024_x_18.ADDRA7 1.313 address<2>.G1 1.464 processor/stack_pop_data<3>.BY address<4> address<4>.XQ 1.828 prog_rom/ram_1024_x_18.ADDRA8 0.524 address<4>.F1 2.200 processor/stack_pop_data<4>.BY address<5> address<4>.YQ 1.854 prog_rom/ram_1024_x_18.ADDRA9 0.812 address<4>.G1 1.455 processor/stack_pop_data<5>.BY address<6> address<6>.XQ 1.280 prog_rom/ram_1024_x_18.ADDRA10 0.801 address<6>.F1 2.095 processor/stack_pop_data<6>.BY address<7> address<6>.YQ 1.289 prog_rom/ram_1024_x_18.ADDRA11 0.571 address<6>.G1 2.158 processor/stack_pop_data<7>.BY address<8> address<8>.XQ 1.267 prog_rom/ram_1024_x_18.ADDRA12 0.536 address<8>.F1 2.053 processor/stack_pop_data<8>.BY address<9> address<8>.YQ 1.629 prog_rom/ram_1024_x_18.ADDRA13 0.535 address<8>.G1 1.636 processor/stack_pop_data<9>.BY clk_BUFGP clk_BUFGP/BUFG.O 0.186 interrupt.ICLK1 0.166 write_strobe.OTCLK1 0.166 read_strobe.OTCLK1 0.150 prog_rom/ram_1024_x_18.CLKA 0.135 processor/store_data<2>.CLK 0.135 processor/memory_bit_2/F5.S1.CLK 0.122 processor/logical_result<7>.CLK 0.143 processor/store_data<7>.CLK 0.143 processor/memory_bit_7/F5.S1.CLK 0.141 processor/store_data<6>.CLK 0.141 processor/memory_bit_6/F5.S1.CLK 0.140 processor/store_data<5>.CLK 0.140 processor/memory_bit_5/F5.S1.CLK 0.137 processor/sy<1>.CLK 0.134 processor/sy<4>.CLK 0.130 processor/sy<6>.CLK 0.130 processor/sy<7>.CLK 0.125 address<0>.CLK 0.125 address<2>.CLK 0.127 address<4>.CLK 0.127 address<6>.CLK 0.128 address<8>.CLK 0.151 processor/stack_pop_data<5>.CLK 0.154 processor/stack_pop_data<9>.CLK 0.137 processor/logical_result<1>.CLK 0.137 processor/shift_result<7>.CLK 0.134 processor/logical_result<4>.CLK 0.134 processor/logical_result<6>.CLK 0.127 processor/carry_flag.CLK 0.128 processor/register_write.CLK 0.147 processor/store_data<3>.CLK 0.147 processor/memory_bit_3/F5.S1.CLK 0.151 processor/store_data<4>.CLK 0.151 processor/memory_bit_4/F5.S1.CLK 0.147 processor/logical_result<3>.CLK 0.147 processor/sy<0>.CLK 0.144 processor/sy<2>.CLK 0.144 processor/sy<3>.CLK 0.141 processor/store_data<1>.CLK 0.141 processor/memory_bit_1/F5.S1.CLK 0.137 processor/store_data<0>.CLK 0.137 processor/memory_bit_0/F5.S1.CLK 0.134 processor/sy<5>.CLK 0.133 processor/shadow_carry.CLK 0.135 processor/active_interrupt.CLK 0.153 processor/sel_group.CLK 0.152 processor/stack_address<0>.CLK 0.152 processor/stack_address<2>.CLK 0.150 processor/stack_address<4>.CLK 0.160 processor/stack_pop_data<3>.CLK 0.149 processor/shift_result<0>.CLK 0.149 processor/shift_result<2>.CLK 0.147 processor/logical_result<0>.CLK 0.147 processor/logical_result<2>.CLK 0.144 processor/arith_result<0>.CLK 0.144 processor/arith_result<1>.CLK 0.141 processor/arith_result<3>.CLK 0.141 processor/arith_result<5>.CLK 0.137 processor/arith_result<7>.CLK 0.134 processor/logical_result<5>.CLK 0.134 interrupt_ack_OBUF.CLK 0.131 processor/shift_result<1>.CLK 0.133 processor/zero_flag.CLK 0.135 processor/flag_write.CLK 0.135 processor/int_enable.CLK 0.175 processor/stack_pop_data<8>.CLK 0.180 processor/stack_pop_data<4>.CLK 0.186 processor/stack_pop_data<0>.CLK 0.188 processor/stack_pop_data<2>.CLK 0.194 processor/stack_pop_data<7>.CLK 0.198 processor/stack_pop_data<6>.CLK 0.200 processor/internal_reset.CLK 0.200 processor/reset_delay.CLK 0.186 processor/stack_pop_data<1>.CLK clk_BUFGP/IBUFG clk.I 0.046 clk_BUFGP/BUFG.I0 in_port_0_IBUF in_port<0>.I 0.878 processor/alu_result<0>.F2 in_port_1_IBUF in_port<1>.I 1.790 processor/alu_result<1>.F2 in_port_2_IBUF in_port<2>.I 0.809 processor/alu_result<2>.F2 in_port_3_IBUF in_port<3>.I 1.053 processor/alu_result<3>.F2 in_port_4_IBUF in_port<4>.I 1.178 interrupt_ack_OBUF.F2 in_port_5_IBUF in_port<5>.I 2.082 processor/alu_result<5>.F2 in_port_6_IBUF in_port<6>.I 2.182 processor/alu_result<6>.F2 in_port_7_IBUF in_port<7>.I 2.493 processor/alu_result<7>.F2 instruction<0> prog_rom/ram_1024_x_18.DOA0 0.666 processor/shift_in.F3 0.831 processor/inc_pc_vector<0>.F2 0.421 processor/logical_result<0>.G2 1.081 processor/int_enable.F3 instruction<10> prog_rom/ram_1024_x_18.DOA10 1.170 processor/sy<1>.G3 1.193 processor/sy<4>.G3 0.893 processor/sy<6>.G3 0.893 processor/sy<7>.G3 0.707 processor/sy<0>.G3 1.244 processor/sy<2>.G3 1.244 processor/sy<3>.G3 0.699 processor/valid_to_move.G3 0.896 processor/sy<5>.G3 instruction<11> prog_rom/ram_1024_x_18.DOA11 0.705 processor/sy<1>.G4 1.036 processor/sy<4>.G4 0.871 processor/sy<6>.G4 0.871 processor/sy<7>.G4 0.952 processor/sy<0>.G4 0.699 processor/sy<2>.G4 0.699 processor/sy<3>.G4 0.491 processor/valid_to_move.G4 0.491 processor/sy<5>.G4 instruction<12> prog_rom/ram_1024_x_18.DOA12 0.983 processor/logical_result<7>.G1 0.891 processor/logical_result<1>.G1 1.088 processor/logical_result<4>.G1 0.690 processor/logical_result<6>.G1 1.274 processor/normal_count.F2 0.970 processor/logical_result<3>.G1 0.476 processor/valid_to_move.F1 1.332 processor/logical_result<0>.G1 0.915 processor/logical_result<2>.G1 0.461 processor/logical_result<5>.G1 instruction<13> prog_rom/ram_1024_x_18.DOA13 0.675 processor/alu_result<6>.F1 1.522 processor/logical_result<7>.F2 1.179 processor/alu_result<5>.F1 1.341 processor/memory_enable.G2 0.986 processor/alu_result<0>.F1 1.089 processor/logical_result<1>.F2 1.083 processor/logical_result<4>.F2 1.083 processor/logical_result<6>.F2 1.120 processor/sel_carry<3>.G3 0.902 processor/alu_result<1>.F1 0.695 processor/alu_result<7>.F1 0.993 processor/alu_result<2>.F1 1.001 processor/logical_result<3>.F2 0.495 processor/inc_pc_vector<0>.BX 1.477 processor/write_active.G2 1.626 processor/logical_result<0>.F2 1.626 processor/logical_result<2>.F2 1.332 processor/arith_result<0>.F1 0.459 processor/logical_result<5>.F2 0.607 interrupt_ack_OBUF.F1 0.552 processor/alu_result<3>.F1 instruction<14> prog_rom/ram_1024_x_18.DOA14 0.960 processor/logical_result<7>.F3 0.771 processor/move_group.F1 1.160 processor/memory_enable.G3 1.547 processor/logical_result<1>.F3 0.728 processor/logical_result<4>.F3 0.728 processor/logical_result<6>.F3 1.539 processor/normal_count.G1 1.435 processor/logical_result<3>.F3 1.389 processor/sel_group.G1 1.058 processor/stack_address<4>.G1 2.105 processor/write_active.G3 1.386 processor/logical_result<0>.F3 0.894 processor/logical_result<2>.F3 1.265 processor/arith_result<0>.F2 1.428 processor/arith_result<0>.G3 1.425 processor/arith_result<1>.F3 1.428 processor/arith_result<1>.G3 0.930 processor/arith_result<3>.F3 0.933 processor/arith_result<3>.G3 0.930 processor/arith_result<5>.F3 0.933 processor/arith_result<5>.G3 0.655 processor/arith_result<7>.F3 0.987 processor/arith_result<7>.G1 0.370 processor/logical_result<5>.F3 0.943 processor/sel_arith.G2 1.193 processor/flag_write.F1 1.570 processor/push_or_pop_type.F1 instruction<15> prog_rom/ram_1024_x_18.DOA15 0.414 processor/move_group.F2 1.080 processor/sel_carry<1>.G2 1.080 processor/sel_carry<3>.G4 0.846 processor/normal_count.G2 1.186 processor/register_write.F2 1.220 processor/register_write.G2 0.568 processor/inc_pc_vector<0>.F1 0.664 processor/inc_pc_vector<0>.G1 0.568 processor/inc_pc_vector<2>.F1 0.608 processor/inc_pc_vector<2>.G1 0.601 processor/shadow_carry.F1 0.701 processor/shadow_carry.G1 0.601 processor/inc_pc_vector<6>.F1 1.169 processor/inc_pc_vector<6>.G1 0.704 processor/inc_pc_vector<8>.F1 1.521 processor/inc_pc_vector<8>.G1 1.402 processor/sel_group.G2 1.666 processor/stack_address<4>.G2 2.819 processor/write_active.F4 0.824 processor/sel_arith.G3 1.589 processor/flag_write.F2 1.630 processor/int_enable.G2 1.320 processor/push_or_pop_type.F2 2.873 processor/read_active.G4 instruction<16> prog_rom/ram_1024_x_18.DOPA0 0.871 processor/move_group.F3 0.999 processor/sel_carry<3>.F2 1.040 processor/sel_carry<3>.G2 1.706 processor/normal_count.G3 2.285 processor/register_write.F3 2.326 processor/register_write.G3 1.394 processor/sel_group.G3 1.657 processor/stack_address<4>.G3 1.873 processor/write_active.G4 1.794 processor/zero_flag.F2 1.770 processor/sel_arith.G1 1.469 processor/flag_write.F3 1.672 processor/int_enable.G3 2.079 processor/push_or_pop_type.F3 instruction<17> prog_rom/ram_1024_x_18.DOPA1 0.660 processor/move_group.F4 1.223 processor/shift_result<7>.SR 0.825 processor/sel_carry<1>.F2 0.653 processor/sel_carry<3>.F3 1.121 processor/normal_count.G4 1.294 processor/register_write.F4 1.270 processor/register_write.G4 1.590 processor/sel_group.G4 1.604 processor/stack_address<4>.G4 2.254 processor/write_active.F2 1.244 processor/shift_result<0>.SR 1.244 processor/shift_result<2>.SR 1.984 processor/shift_result<1>.SR 2.050 processor/zero_flag.F3 1.197 processor/flag_write.F4 1.261 processor/int_enable.G4 1.577 processor/push_or_pop_type.F4 1.915 processor/read_active.G2 instruction<1> prog_rom/ram_1024_x_18.DOA1 0.895 processor/shift_in.F1 1.269 processor/shift_in.G1 0.385 processor/logical_result<1>.G2 0.833 processor/inc_pc_vector<0>.G2 instruction<2> prog_rom/ram_1024_x_18.DOA2 0.713 processor/shift_in.BX 0.825 processor/inc_pc_vector<2>.F2 0.944 processor/logical_result<2>.G2 instruction<3> prog_rom/ram_1024_x_18.DOA3 0.370 processor/shift_result<7>.F1 0.404 processor/shift_result<7>.G1 0.453 processor/logical_result<3>.G2 0.877 processor/inc_pc_vector<2>.G2 0.647 processor/shift_result<0>.F1 1.098 processor/shift_result<0>.G1 0.647 processor/shift_result<2>.F1 0.681 processor/shift_result<2>.G1 0.955 processor/shift_result<1>.F1 0.931 processor/shift_result<1>.G1 1.136 processor/flag_write.G1 instruction<4> prog_rom/ram_1024_x_18.DOA4 0.713 processor/sy<1>.F1 0.488 processor/sy<4>.F1 0.729 processor/sy<6>.F1 0.729 processor/sy<7>.F1 0.704 processor/logical_result<4>.G2 0.734 processor/sy<0>.F1 0.523 processor/sy<2>.F1 0.523 processor/sy<3>.F1 0.703 processor/sy<5>.F1 0.854 processor/shadow_carry.F2 instruction<5> prog_rom/ram_1024_x_18.DOA5 0.961 processor/sy<1>.F2 0.734 processor/sy<4>.F2 0.717 processor/sy<6>.F2 0.717 processor/sy<7>.F2 0.652 processor/sy<0>.F2 0.699 processor/sy<2>.F2 0.699 processor/sy<3>.F2 0.971 processor/sy<5>.F2 0.871 processor/shadow_carry.G2 0.802 processor/logical_result<5>.G2 instruction<6> prog_rom/ram_1024_x_18.DOA6 0.613 processor/sy<1>.F3 0.653 processor/sy<4>.F3 0.620 processor/sy<6>.F3 0.620 processor/sy<7>.F3 0.395 processor/logical_result<6>.G2 0.905 processor/sy<0>.F3 0.425 processor/sy<2>.F3 0.425 processor/sy<3>.F3 0.592 processor/sy<5>.F3 0.891 processor/inc_pc_vector<6>.F2 instruction<7> prog_rom/ram_1024_x_18.DOA7 0.950 processor/logical_result<7>.G2 0.608 processor/sy<1>.F4 0.369 processor/sy<4>.F4 0.623 processor/sy<6>.F4 0.623 processor/sy<7>.F4 0.580 processor/sy<0>.F4 0.602 processor/sy<2>.F4 0.617 processor/sy<3>.F4 0.619 processor/sy<5>.F4 0.923 processor/inc_pc_vector<6>.G2 instruction<8> prog_rom/ram_1024_x_18.DOA8 0.953 processor/sy<1>.G1 0.970 processor/sy<4>.G1 0.978 processor/sy<6>.G1 0.978 processor/sy<7>.G1 1.249 processor/sy<0>.G1 1.157 processor/sy<2>.G1 1.157 processor/sy<3>.G1 0.672 processor/sy<5>.G1 0.923 processor/inc_pc_vector<8>.F2 instruction<9> prog_rom/ram_1024_x_18.DOA9 0.717 processor/sy<1>.G2 1.546 processor/sy<4>.G2 1.089 processor/sy<6>.G2 1.089 processor/sy<7>.G2 0.961 processor/sy<0>.G2 0.709 processor/sy<2>.G2 0.709 processor/sy<3>.G2 1.363 processor/sy<5>.G2 1.033 processor/inc_pc_vector<8>.G2 interrupt_ack_OBUF interrupt_ack_OBUF.YQ 1.340 interrupt_ack.O1 0.916 processor/int_enable.F1 out_port_0_OBUF processor/sy<0>.Y 1.717 out_port<0>.O1 0.395 processor/shift_in.F2 1.626 processor/memory_bit_0/F5.S1.BY 0.146 processor/logical_result<0>.F1 0.772 processor/arith_result<0>.G1 0.756 processor/shift_result<1>.F2 0.760 processor/flag_write.G3 out_port_1_OBUF processor/sy<1>.Y 1.373 out_port<1>.O1 0.158 processor/logical_result<1>.F1 0.498 processor/memory_bit_1/F5.S1.BY 0.734 processor/shift_result<0>.F2 0.950 processor/shift_result<2>.F2 0.540 processor/arith_result<1>.F1 out_port_2_OBUF processor/sy<2>.Y 1.272 out_port<2>.O1 0.959 processor/memory_bit_2/F5.S1.BY 0.488 processor/logical_result<2>.F1 0.239 processor/arith_result<1>.G1 0.583 processor/shift_result<1>.F3 0.617 processor/shift_result<1>.G2 out_port_3_OBUF processor/sy<3>.Y 1.429 out_port<3>.O1 1.204 processor/memory_bit_3/F5.S1.BY 0.410 processor/logical_result<3>.F1 0.875 processor/shift_result<2>.F3 0.851 processor/shift_result<2>.G2 0.413 processor/arith_result<3>.F1 out_port_4_OBUF processor/sy<4>.Y 1.140 out_port<4>.O1 0.167 processor/logical_result<4>.F1 1.032 processor/memory_bit_4/F5.S1.BY 0.716 processor/shift_result<0>.G2 0.505 processor/arith_result<3>.G1 0.947 processor/shift_result<1>.G3 out_port_5_OBUF processor/sy<5>.Y 1.460 out_port<5>.O1 1.641 processor/memory_bit_5/F5.S1.BY 0.611 processor/shift_result<7>.G2 0.892 processor/shift_result<2>.G3 0.441 processor/arith_result<5>.F1 0.179 processor/logical_result<5>.F1 out_port_6_OBUF processor/sy<6>.Y 1.163 out_port<6>.O1 0.756 processor/memory_bit_6/F5.S1.BY 0.428 processor/shift_result<7>.F2 0.421 processor/logical_result<6>.F1 0.843 processor/shift_result<0>.G3 0.759 processor/arith_result<5>.G1 out_port_7_OBUF processor/sy<7>.Y 1.189 out_port<7>.O1 0.451 processor/logical_result<7>.F1 1.348 processor/memory_bit_7/F5.S1.BY 0.760 processor/shift_in.G3 1.288 processor/shift_result<7>.G3 0.490 processor/arith_result<7>.F1 0.950 processor/flag_write.G2 port_id_0_OBUF processor/logical_result<0>.Y 1.495 port_id<0>.O1 1.031 processor/store_data<2>.F1 1.036 processor/store_data<2>.G1 1.031 processor/memory_bit_2/F5.S1.F1 1.036 processor/memory_bit_2/F5.S1.G1 1.076 processor/store_data<7>.F1 1.007 processor/store_data<7>.G1 1.002 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(всё не вместилось) Изменено 22 мая, 2007 пользователем ClockworkOrange Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
makc 207 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба 1. Можно было заархивировать и прикрепить архив к сообщению. 2. В приведенном репорте ни слова нет про нарушение временных ограничений (timing constraints). В Вашем проекте есть timing constraints? Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
ClockworkOrange 0 22 мая, 2007 Опубликовано 22 мая, 2007 · Жалоба *.UCF: NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 8 ns HIGH 50 %; TEMPERATURE=25 C; VOLTAGE=1.2 V; *.PAR: Release 8.2.03i par I.34 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. Tue May 22 21:22:12 2007 par -w -intstyle ise -pl high -rl high -t 1 embedded_kcpsm3_map.ncd embedded_kcpsm3.ncd embedded_kcpsm3.pcf Constraints file: embedded_kcpsm3.pcf. Loading device for application Rf_Device from file '3s500e.nph' in environment C:\prog\ise. "embedded_kcpsm3" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4 Initializing temperature to 25.000 Celsius. (derated - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.200 Volts. (derated - Range: 1.140 to 1.320 Volts) Device speed data version: "PRODUCTION 1.26 2006-08-18". ..... .... ... Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX_X2Y10| No | 81 | 0.074 | 0.190 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 1.073 The MAXIMUM PIN DELAY IS: 4.914 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.413 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 550 270 99 29 8 0 Timing Score: 3748 INFO:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and select the "Timing Improvement Wizard" link for suggestions to correct each problem. Increase the PAR Effort Level setting to "high" Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" (ISE process "Multi Pass Place & Route"). Use the Xilinx "xplorer" script to try special combinations of options known to produce very good results. See http://www.xilinx.com/xplorer for details. Visit the Xilinx technical support web at http://support.xilinx.com and go to either "Troubleshoot->Tech Tips->Timing & Constraints" or " TechXclusives->Timing Closure" for tips and suggestions for meeting timing in your design. Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------ * TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 5 | 8.000ns | 8.475ns | 5 | -0.475ns | 20 0% | | | | | ------------------------------------------------------------------------------------------------------ 1 constraint not met PAR done! Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
makc 207 23 мая, 2007 Опубликовано 23 мая, 2007 · Жалоба Уже лучше, но опять не все. Не хватает Static Timing Report'a, в котором можно было бы посмотреть компоненты возникающей задержки и выяснить ее причины. Сразу скажу, что если задержки трассировки (routing delay) превышают задержки логических элементов, то можно попробовать прислушаться к советам Xilinxовского PAR: Increase the PAR Effort Level setting to "high" Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" (ISE process "Multi Pass Place & Route"). Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
3.14 0 23 мая, 2007 Опубликовано 23 мая, 2007 · Жалоба Хочу добавить, поведение констрейнов температуры и питания ядра непонятно для разных чипов. Например, одни и те же ограничения работают на Spartan2 и игнорируются на Spartan3, Spartan3E, в причинах не разбирался. В частности с вашими временными ошибками (насколько я понял это Вы PicoBlaze собираете), это особо не ошибка, можно смело продолжать работу над проектом, а в конце небольшим танцем с бубном выровнять ситуацию - напимер, растолкать части по AREA (если до этого не сделали) и потаскать их туда сюда по кристаллу, MPPR и т.п. Кострейн напряжения ядра (если заработает), то же должен помочь, по крайней мере на Spartan2 в "глухих" случаях "вытягивал" до 1.5 нс. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
ClockworkOrange 0 23 мая, 2007 Опубликовано 23 мая, 2007 · Жалоба >> насколько я понял это Вы PicoBlaze собираете да . это стандартный проект PicoBlaze: ядро KCPSM3 + память блочная. >> Increase the PAR Effort Level setting to "high" включено было сразу. >> Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" попробовть конечно можно, но: 1) всеже такая рекомендация имхо применима для сложных случаев, а не когда на кристалле задействовано всего 2% логики 2) все больше отклоняемся от темы: данный проект - частность, пример.. Хотелось бы понять всеже как заставить ISE проводить временной анализ исходя из заданных пользователем T и V. >> Не хватает Static Timing Report'a analyse .ncd : -------------------------------------------------------------------------------- Release 8.2.03i Trace Copyright © 1995-2006 Xilinx, Inc. All rights reserved. ise -e 3 -l 3 -s 4 -xml embedded_kcpsm3 embedded_kcpsm3.ncd -o embedded_kcpsm3.twr embedded_kcpsm3.pcf -ucf kcpsm3_int_test.ucf Design file: embedded_kcpsm3.ncd Physical constraint file: embedded_kcpsm3.pcf Device,speed: xc3s500e,-4 (PRODUCTION 1.26 2006-08-18) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. Derating parameters ------------------- Temperature: 25 C Voltage: 1.200 V ================================================================================ Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 8 ns HIGH 50%; 5613 items analyzed, 20 timing errors detected. (20 setup errors, 0 hold errors) Minimum period is 8.475ns. -------------------------------------------------------------------------------- Slack: -0.475ns (requirement - (data path - clock path skew + uncertainty)) Source: prog_rom/ram_1024_x_18.A (RAM) Destination: processor/arith_carry_flop (FF) Requirement: 8.000ns Data Path Delay: 8.454ns (Levels of Logic = 5) Clock Path Skew: -0.021ns Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 8.000ns Clock Uncertainty: 0.000ns Timing Improvement Wizard Data Path: prog_rom/ram_1024_x_18.A to processor/arith_carry_flop Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tbcko 2.784 prog_rom/ram_1024_x_18.A net (fanout=10) 0.691 instruction<4> Tilo 0.751 processor/reg_loop_register_bit_3.SLICEM_F net (fanout=1) 0.714 processor/sy<3> Tilo 0.751 processor/operand_select_mux_3 net (fanout=35) 0.504 port_id_3_OBUF Topcyf 1.150 processor/arith_lut_3 processor/arith_muxcy_3 processor/arith_muxcy_4 net (fanout=1) 0.000 processor/arith_internal_carry<4> Tbyp 0.117 processor/arith_muxcy_5 processor/arith_muxcy_6 net (fanout=1) 0.000 processor/arith_internal_carry<6> Tcinck 0.992 processor/arith_muxcy_7 processor/arith_carry_out_xor processor/arith_carry_flop ---------------------------- --------------------------- Total 8.454ns (6.545ns logic, 1.909ns route) (77.4% logic, 22.6% route) -------------------------------------------------------------------------------- Slack: -0.469ns (requirement - (data path - clock path skew + uncertainty)) Source: prog_rom/ram_1024_x_18.A (RAM) Destination: processor/arith_carry_flop (FF) Requirement: 8.000ns Data Path Delay: 8.448ns (Levels of Logic = 3) Clock Path Skew: -0.021ns Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 8.000ns Clock Uncertainty: 0.000ns Timing Improvement Wizard Data Path: prog_rom/ram_1024_x_18.A to processor/arith_carry_flop Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tbcko 2.784 prog_rom/ram_1024_x_18.A net (fanout=10) 1.044 instruction<5> Tilo 0.751 processor/reg_loop_register_bit_7.SLICEM_F net (fanout=1) 1.009 processor/sy<7> Tilo 0.697 processor/operand_select_mux_7 net (fanout=3) 0.407 port_id_7_OBUF Tfck 1.756 processor/arith_lut_7 processor/arith_muxcy_7 processor/arith_carry_out_xor processor/arith_carry_flop ---------------------------- --------------------------- Total 8.448ns (5.988ns logic, 2.460ns route) (70.9% logic, 29.1% route) -------------------------------------------------------------------------------- Slack: -0.420ns (requirement - (data path - clock path skew + uncertainty)) Source: prog_rom/ram_1024_x_18.A (RAM) Destination: processor/arith_carry_flop (FF) Requirement: 8.000ns Data Path Delay: 8.399ns (Levels of Logic = 5) Clock Path Skew: -0.021ns Source Clock: clk_BUFGP rising at 0.000ns Destination Clock: clk_BUFGP rising at 8.000ns Clock Uncertainty: 0.000ns Timing Improvement Wizard Data Path: prog_rom/ram_1024_x_18.A to processor/arith_carry_flop Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tbcko 2.784 prog_rom/ram_1024_x_18.A net (fanout=10) 0.636 instruction<6> Tilo 0.751 processor/reg_loop_register_bit_3.SLICEM_F net (fanout=1) 0.714 processor/sy<3> Tilo 0.751 processor/operand_select_mux_3 net (fanout=35) 0.504 port_id_3_OBUF Topcyf 1.150 processor/arith_lut_3 processor/arith_muxcy_3 processor/arith_muxcy_4 net (fanout=1) 0.000 processor/arith_internal_carry<4> Tbyp 0.117 processor/arith_muxcy_5 processor/arith_muxcy_6 net (fanout=1) 0.000 processor/arith_internal_carry<6> Tcinck 0.992 processor/arith_muxcy_7 processor/arith_carry_out_xor processor/arith_carry_flop ---------------------------- --------------------------- Total 8.399ns (6.545ns logic, 1.854ns route) (77.9% logic, 22.1% route) -------------------------------------------------------------------------------- 1 constraint not met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk | 8.475| | | | ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 20 Score: 3748 Constraints cover 5613 paths, 0 nets, and 939 connections Analysis completed Wed May 23 10:18:33 2007 Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
3.14 0 23 мая, 2007 Опубликовано 23 мая, 2007 · Жалоба Сори, сразу не разглядел в вашем PAR отчете (вернее не то увидел :)) >>Initializing temperature to 25.000 Celsius. (derated - Range: -40.000 to 100.000 Celsius) >>Initializing voltage to 1.200 Volts. (derated - Range: 1.140 to 1.320 Volts) Вот эти самые строчки говорят что VOLTAGE и TEMPERATURE сработали как надо, ради спортивного интереса уберите и эти констрейны и увидите разницу. Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
ClockworkOrange 0 23 мая, 2007 Опубликовано 23 мая, 2007 · Жалоба >> Вот эти самые строчки говорят что VOLTAGE и TEMPERATURE сработали как надо, >> ради спортивного интереса уберите и эти констрейны и увидите разницу. к сожалению, нету разницы((( что с ними, что без них железно получаю 8.475ns действительно ISE для S3E как-то по-особому обрабатывает ситуацию с констрейнами V и T Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
rloc 49 23 мая, 2007 Опубликовано 23 мая, 2007 · Жалоба это стандартный проект PicoBlaze: ядро KCPSM3 + память блочная. >> Не хватает Static Timing Report'a analyse .ncd : Data Path: prog_rom/ram_1024_x_18.A to processor/arith_carry_flop Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tbcko 2.784 prog_rom/ram_1024_x_18.A net (fanout=10) 0.691 instruction<4> Никогда не работал с PicoBlaze, но судя по Static Timing Report's, здесь явно не хватает регистра по выходу этой блочной памяти, все проблемы решатся с большим запасом! Цитата Поделиться сообщением Ссылка на сообщение Поделиться на другие сайты Поделиться
