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Доброго всем. Заказчик (Азия) ищет консультанта на проект с OpenCL (FPGA платформа). Ниже список вопросов. Если есть компетенция в данном hardware, напишите в личку - дам контакты заказчика. Queries related to programming PAC Card/A10 Dev Kits - We are trying to compile RTL level design and test it on A10 PAC card. But Intel doesn't share the pin assignment details. How should we proceed further? - How can we enable the IO channels in the OpenCL BSP of Arria 10? - Can we make changes to BSP of Arria 10 PAC card? - How to configure intel Arria 10 Development kit through PCIe to run the OpenCL based applications. Queries related to FPGA Package/configuration/testing - JTAG issue : The Devkit doesn't get detected on HostPCs frequently. "No USB Blaster is detected" - Which Tools to work on baredie FPGA because in Quartus, it asks us to specify the exact device name - but package part cannot be selected for a bare-die. - How can we get Information about the additional banks(2F, 2G, 2H) which are available in baredie? How should I connect/terminate/float them? - We are using the Early Power Estimator sheet to get information about power requirements for the FPGA. When all the available resources are used, Why is the current rating different in EPE and reference power tree(A10 DevKit)? Why is this change and which to refer? - How complicated will it be to interface an external processor with an FPGA (or two FPGAs) through PCIe switch - We are using CPLD( for temp and voltage monitoring) and a processor - Can we replace both with Cyclone 10 or any other FPGA? will it be a good choice? - There is no Eye Viewer support for Arria 10 as ODI - On die Instrumentation is not available. Is there any tool in Intel using which we can get the Eye Viewer. It will be helpful. Queries regarding Intel device plugins for kubernetes.