asen 0 15 июня, 2017 Опубликовано 15 июня, 2017 · Жалоба :1111493779: Добрый день Начал делать проект на контроллере MKV58 у него ацп HSADC0 (как и HSadc1) имеет два модуля A и Б каждый на входе имеет два мультиплексора последовательно. На входе первого уровня мультиплексор коммутирует с 0-7 канал измерение через этот мультиплексор на данные идут нормально от каналов 0-5 а к 6 и 7 каналу подключен мультиплексор второго уровня который переключает каналы с 6 по 15 и вот от этих каналов данные идут с смещением или вообще не корректные. Побывал даже пример из SDK по работе HSADC результат тот же. Проверял режимы как последовательно так и параллельного измерения. Что-то тут не чисто. Может кто-то делал измерения или имеет демо плату проверить с таким процом?? Нужно измерить через два мультиплексора сигнал с каналов от 6 и выше (может они еще называются 6A или 7A и выше ) и убедится в чем беда. Еще заметил что когда в дебагере пройдет цикл опроса всех входов и остановится на брек поите на последнем каждой секции (А и Б) канале мультиплексора на ноге входа весит напряжение около 2.5 вольта как из входа вытекает напряжение ? проц менял 3 раза уж. Режим тактирования HSRUN всегда #include "fsl_debug_console.h" #include "board.h" #include "fsl_hsadc.h" #include "pin_mux.h" #include "fsl_common.h" /******************************************************************************* * Definitions ******************************************************************************/ /* HSADC base address. */ #define DEMO_HSADC_INSTANCE HSADC0 /* Following macros define the channels which will be sampled in the example. * Note that there are 2 kinds of configuration combination: * 1) DEMO_HSADC_CONV_CHN_NUM isn't 6 or 7; * DEMO_HSADC_CONV_CHN_NUM must be configured to the value in the range 0~5; * DEMO_HSADC_CONV_CHN67_MUX_NUM won't be functional and can be configured to any value. * 2) DEMO_HSADC_CONV_CHN_NUM is 6 or 7; * DEMO_HSADC_CONV_CHN67_MUX_NUM must be configured to the value in the range 0~6. * No mater what kind of configuration combination, two adjacent channels will be sampled in differential mode if * DEMO_HSADC_CONV_CHN_NUM_ENABLE_DIFF is true. */ /* The converter A's channels to sample. */ #define DEMO_HSADC_CONVA_CHN_NUM1 3U /* Configuration combination 1, ADCA_CH2 and ADCA_CH3 */ #define DEMO_HSADC_CONVA_CHN67_MUX_NUM1 0U #define DEMO_HSADC_CONVA_CHN_NUM1_ENABLE_DIFF false #define DEMO_HSADC_CONVA_CHN_NUM2 6U /* Configuration combination 2, ADCA_CH6D */ #define DEMO_HSADC_CONVA_CHN67_MUX_NUM2 2U #define DEMO_HSADC_CONVA_CHN_NUM2_ENABLE_DIFF false /* The converter B's channels to sample. */ #define DEMO_HSADC_CONVB_CHN_NUM1 6U /* Configuration combination 2, ADCB_CH6C(PTE2) */ #define DEMO_HSADC_CONVB_CHN67_MUX_NUM1 2U #define DEMO_HSADC_CONVB_CHN_NUM1_ENABLE_DIFF false #define DEMO_HSADC_CONVB_CHN_NUM2 7U /* Configuration combination 2, ADCB_CH7F(PTE1) */ #define DEMO_HSADC_CONVB_CHN67_MUX_NUM2 2U #define DEMO_HSADC_CONVB_CHN_NUM2_ENABLE_DIFF false /******************************************************************************* * Prototypes ******************************************************************************/ /******************************************************************************* * Variables ******************************************************************************/ /******************************************************************************* * Code ******************************************************************************/ /*! * @brief Main function */ int main(void) { hsadc_config_t hsadcConfigStruct; hsadc_converter_config_t hsadcConverterConfigStruct; hsadc_sample_config_t hsadcSampleConfigStruct; uint16_t sampleMask; BOARD_InitPins(); BOARD_BootClockHSRUN(); BOARD_InitDebugConsole(); PRINTF("HSADC dual parallel conversion example.\r\n"); /* Initialize the HSADC common digital control. * "kHSADC_DualConverterWorkAsTriggeredParallel" and simultaneous mode is used in this case. The two conversion * sequence would be executed by each converter at the same time. Both converter shares the converter A's control * logic such as start, stop, DMA enable, sync input etc. */ HSADC_GetDefaultConfig(&hsadcConfigStruct); HSADC_Init(DEMO_HSADC_INSTANCE, &hsadcConfigStruct); /* Configure each converter. */ HSADC_GetDefaultConverterConfig(&hsadcConverterConfigStruct); /* Enable the calibration in power up period. */ hsadcConverterConfigStruct.clockDivisor= 9; hsadcConverterConfigStruct.samplingTimeCount =250; hsadcConverterConfigStruct.powerUpCalibrationModeMask = (kHSADC_CalibrationModeSingleEnded | kHSADC_CalibrationModeDifferential); HSADC_SetConverterConfig(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, &hsadcConverterConfigStruct); /* Enable the power for each converter. */ HSADC_EnableConverterPower(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, true); while ( (kHSADC_ConverterAPowerDownFlag | kHSADC_ConverterBPowerDownFlag) == ((kHSADC_ConverterAPowerDownFlag | kHSADC_ConverterBPowerDownFlag) & HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE))) { } /* Wait the calibration process complete. None End of Scan flag will be set after power up calibration process. */ while ((kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag) != ((kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag) & HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE))) { } HSADC_ClearStatusFlags(DEMO_HSADC_INSTANCE, (kHSADC_ConverterAEndOfCalibrationFlag | kHSADC_ConverterBEndOfCalibrationFlag)); /* Make each converter exit stop mode. */ HSADC_EnableConverter(DEMO_HSADC_INSTANCE, kHSADC_ConverterA | kHSADC_ConverterB, true); /* Configure the samples. */ HSADC_GetDefaultSampleConfig(&hsadcSampleConfigStruct); /* For converter A. */ hsadcSampleConfigStruct.channelNumber = DEMO_HSADC_CONVA_CHN_NUM1; hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVA_CHN67_MUX_NUM1; hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVA_CHN_NUM1_ENABLE_DIFF; HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 0U, &hsadcSampleConfigStruct); hsadcSampleConfigStruct.channelNumber = DEMO_HSADC_CONVA_CHN_NUM2; hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVA_CHN67_MUX_NUM2; hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVA_CHN_NUM2_ENABLE_DIFF; HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 1U, &hsadcSampleConfigStruct); /* For converter B. * In HSADC_SetSampleConfig(), the channel number 0~7 represents input 0~7 of converter A and channel number 8~15 * represents input 0~7 of converter B. */ hsadcSampleConfigStruct.channelNumber = (DEMO_HSADC_CONVB_CHN_NUM1 + 8U); hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVB_CHN67_MUX_NUM1; hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVB_CHN_NUM1_ENABLE_DIFF; HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 8U, &hsadcSampleConfigStruct); hsadcSampleConfigStruct.channelNumber = (DEMO_HSADC_CONVB_CHN_NUM2 + 8U); hsadcSampleConfigStruct.channel67MuxNumber = DEMO_HSADC_CONVB_CHN67_MUX_NUM2; hsadcSampleConfigStruct.enableDifferentialPair = DEMO_HSADC_CONVB_CHN_NUM2_ENABLE_DIFF; HSADC_SetSampleConfig(DEMO_HSADC_INSTANCE, 9U, &hsadcSampleConfigStruct); /* Enable the sample slot. * The conversion sequence for converter A includes sample slot 0 and 1, while the sequence for converter B * includes sample slot 8 and 9. Sample slot 0~7 can reference only to converter A and sample slot 8~15 can * reference only to converter B in parallel mode. */ sampleMask = HSADC_SAMPLE_MASK(0U) /* For converter A. */ | HSADC_SAMPLE_MASK(1U) /* For converter A. */ | HSADC_SAMPLE_MASK(8U) /* For converter B. */ | HSADC_SAMPLE_MASK(9U); /* For converter B. */ HSADC_EnableSample(DEMO_HSADC_INSTANCE, sampleMask, true); HSADC_EnableSample(DEMO_HSADC_INSTANCE, (uint16_t)(~sampleMask), false); /* Disable other sample slots. */ PRINTF("Press any key to trigger the conversion ...\r\n"); PRINTF("\r\nSample 0\tSample 1\tSample 8\tSample 9\r\n"); while (true) { PRINTF("\r\n"); /* Trigger the converter. * Trigger converter A would execute both converter's conversion when in * "kHSADC_DualConverterWorkAsTriggeredParallel" and simultaneous work mode. */ /// GETCHAR(); HSADC_DoSoftwareTriggerConverter(DEMO_HSADC_INSTANCE, kHSADC_ConverterA); /* Wait the conversion to be done. */ while (kHSADC_ConverterAEndOfScanFlag != (kHSADC_ConverterAEndOfScanFlag & HSADC_GetStatusFlags(DEMO_HSADC_INSTANCE))) { } /* Read the result value. */ if (sampleMask == (sampleMask & HSADC_GetSampleReadyStatusFlags(DEMO_HSADC_INSTANCE))) { PRINTF("%d\t\t", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 0U)); PRINTF("%d\t\t", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 1U)); PRINTF("%d\t\t", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 8U)); PRINTF("%d", (int16_t)HSADC_GetSampleResultValue(DEMO_HSADC_INSTANCE, 9U)); } HSADC_ClearStatusFlags(DEMO_HSADC_INSTANCE, kHSADC_ConverterAEndOfScanFlag); } } вот инит клока процессора кварц 25MHz /* * How to setup clock using clock driver functions: * * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock * and flash clock are in allowed range during clock mode switch. * * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode. * * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and * internal reference clock(MCGIRCLK). Follow the steps to setup: * * 1). Call CLOCK_BootToXxxMode to set MCG to target mode. * * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig * explicitly to setup MCGIRCLK. * * 3). Don't need to configure FLL explicitly, because if target mode is FLL * mode, then FLL has been configured by the function CLOCK_BootToXxxMode, * if the target mode is not FLL mode, the FLL is disabled. * * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could * be enabled independently, call CLOCK_EnablePll0 explicitly in this case. * * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM. */ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo product: Clocks v3.0 processor: MKV58F1M0xxx24 package_id: MKV58F1M0VLQ24 mcu_data: ksdk2_0 processor_version: 2.0.0 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ #include "fsl_smc.h" #include "clock_config.h" /******************************************************************************* * Definitions ******************************************************************************/ #define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */ #define SIM_ENET_RMII_CLK_SEL_CLKIN_CLK 1U /*!< SDHC clock select: CLKIN (External bypass clock) */ #define SIM_OSC32KSEL_LPO_CLK 3U /*!< OSC32KSEL select: LPO clock */ #define SIM_PLLFLLSEL_MCGPLLCLK_CLK 1U /*!< PLLFLL select: MCGPLLCLK clock */ /******************************************************************************* * Variables ******************************************************************************/ /* System clock frequency. */ extern uint32_t SystemCoreClock; /******************************************************************************* * Code ******************************************************************************/ /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetSimSafeDivs * Description : This function sets the system clock dividers in SIM to safe * value. * *END**************************************************************************/ static void CLOCK_CONFIG_SetSimSafeDivs(void) { SIM->CLKDIV1 = 0x01170000U; } /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetFllExtRefDiv * Description : Configure FLL external reference divider (FRDIV). * Param frdiv : The value to set FRDIV. * *END**************************************************************************/ static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv) { MCG->C1 = ((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv)); } /*FUNCTION********************************************************************** * * Function Name : CLOCK_CONFIG_SetRmii0Clock * Description : Set RMII clock source. * Param src : The value to set RMII clock source. * *END**************************************************************************/ static void CLOCK_CONFIG_SetRmii0Clock(uint32_t src) { SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RMIISRC_MASK) | SIM_SOPT2_RMIISRC(src)); } /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ void BOARD_InitBootClocks(void) { } /******************************************************************************* ********************* Configuration BOARD_BootClockHSRUN ********************** ******************************************************************************/ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!Configuration name: BOARD_BootClockHSRUN outputs: - {id: Bus_clock.outFreq, value: 100 MHz} - {id: Core_clock.outFreq, value: 200 MHz} - {id: ERCLK32K.outFreq, value: 1 kHz} - {id: Flash_clock.outFreq, value: 25 MHz} - {id: FlexBus_clock.outFreq, value: 50 MHz} - {id: LPO_clock.outFreq, value: 1 kHz} - {id: MCGFFCLK.outFreq, value: 195.3125 kHz} - {id: NANOEDGE2XCLK.outFreq, value: 200 MHz} - {id: OSCERCLK.outFreq, value: 25 MHz} - {id: OSCERCLK_UNDIV.outFreq, value: 25 MHz} - {id: PLLFLLCLK.outFreq, value: 200 MHz} - {id: RMIICLK.outFreq, value: 50 MHz} - {id: System_clock.outFreq, value: 200 MHz} settings: - {id: MCGMode, value: PEE} - {id: powerMode, value: HSRUN} - {id: MCG.FCRDIV.scale, value: '1', locked: true} - {id: MCG.FLL_mul.scale, value: '2197', locked: true} - {id: MCG.FRDIV.scale, value: '128', locked: true} - {id: MCG.IRCS.sel, value: MCG.FCRDIV} - {id: MCG.IREFS.sel, value: MCG.FRDIV} - {id: MCG.PLLS.sel, value: MCG.PLL_DIV2} - {id: MCG.PRDIV.scale, value: '2', locked: true} - {id: MCG.VDIV.scale, value: '32', locked: true} - {id: MCG_C2_OSC_MODE_CFG, value: ModeOscLowPower} - {id: MCG_C2_RANGE0_CFG, value: Very_high} - {id: MCG_C2_RANGE0_FRDIV_CFG, value: Very_high} - {id: MCG_C5_PLLCLKEN0_CFG, value: Enabled} - {id: MCG_C5_PLLSTEN0_CFG, value: Enabled} - {id: NANOEDGE2XClkConfig, value: 'yes'} - {id: OSC_CR_ERCLKEN_CFG, value: Enabled} - {id: OSC_CR_ERCLKEN_UNDIV_CFG, value: Enabled} - {id: OSC_CR_EREFSTEN_CFG, value: Enabled} - {id: OSC_CR_EREFSTEN_UNDIV_CFG, value: Enabled} - {id: OSC_CR_SYS_OSC_CAP_LOAD_CFG, value: SC10PF} - {id: RMIISrcConfig, value: 'yes'} - {id: SIM.OSC32KSEL.sel, value: PMC.LPOCLK} - {id: SIM.OUTDIV1.scale, value: '1', locked: true} - {id: SIM.OUTDIV2.scale, value: '2', locked: true} - {id: SIM.OUTDIV3.scale, value: '4', locked: true} - {id: SIM.OUTDIV4.scale, value: '8', locked: true} - {id: SIM.PLLFLLSEL.sel, value: MCG.MCGPLLCLK} - {id: SIM.RMIICLKSEL.sel, value: SIM.ENET_1588_CLK_EXT} - {id: SIM.TIMESRCSEL.sel, value: SIM.ENET_1588_CLK_EXT} sources: - {id: MCG.FAST_IRCLK.outFreq, value: 5 MHz} - {id: OSC.OSC.outFreq, value: 25 MHz, enabled: true} - {id: SIM.ENET_1588_CLK_EXT.outFreq, value: 50 MHz, enabled: true} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ /******************************************************************************* * Variables for BOARD_BootClockHSRUN configuration ******************************************************************************/ const mcg_config_t mcgConfig_BOARD_BootClockHSRUN = { .mcgMode = kMCG_ModePEE, /* PEE - PLL Engaged External */ .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */ .ircs = kMCG_IrcFast, /* Fast internal reference clock selected */ .fcrdiv = 0x0U, /* Fast IRC divider: divided by 1 */ .frdiv = 0x2U, /* FLL reference clock divider: divided by 128 */ .drs = kMCG_DrsMidHigh, /* Mid-High frequency range */ .dmx32 = kMCG_Dmx32Fine, /* DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ .pll0Config = { .enableMode = kMCG_PllEnableIndependent | kMCG_PllEnableInStop,/* MCGPLLCLK enabled independently of MCG clock mode as well as in STOP mode */ .prdiv = 0x1U, /* PLL Reference divider: divided by 2 */ .vdiv = 0x10U, /* VCO divider: multiplied by 32 */ }, }; const sim_clock_config_t simConfig_BOARD_BootClockHSRUN = { .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */ .er32kSrc = SIM_OSC32KSEL_LPO_CLK, /* OSC32KSEL select: LPO clock */ .clkdiv1 = 0x1370000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /4, OUTDIV4: /8 */ }; const osc_config_t oscConfig_BOARD_BootClockHSRUN = { .freq = 25000000U, /* Oscillator frequency: 25000000Hz */ .capLoad = (kOSC_Cap2P | kOSC_Cap8P), /* Oscillator capacity load: 10pF */ .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */ .oscerConfig = { .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,/* Enable external reference clock, enable external reference clock in STOP mode */ .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */ } }; /******************************************************************************* * Code for BOARD_BootClockHSRUN configuration ******************************************************************************/ void BOARD_BootClockHSRUN(void) { /* Set HSRUN power mode */ SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll); SMC_SetPowerModeHsrun(SMC); while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun) { } /* Set the system clock dividers in SIM to safe value. */ CLOCK_CONFIG_SetSimSafeDivs(); /* Initializes OSC0 according to board configuration. */ CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN); CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq); /* Configure FLL external reference divider (FRDIV). */ CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv); /* Set MCG to PEE mode. */ CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &mcgConfig_BOARD_BootClockHSRUN.pll0Config); /* Set the clock configuration in SIM module. */ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN); /* Set SystemCoreClock variable. */ SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK; /* Set RMII clock source. */ CLOCK_CONFIG_SetRmii0Clock(SIM_ENET_RMII_CLK_SEL_CLKIN_CLK); } Как может это прокомментировать ? почему мерится через первый MUX и не мерится через второй ?? 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