[gosha 0]

Symplify Pro 2013 игнорирует указание top_module (верхнего модуля).

 

Mixed проект vhdl+verilog.

 

В проекте AHDL указываю top_module= cpm_top

В synthesis order указываю синтезировать top.v последним

 

Еще до просмотра .v файлов symplify решает, что файл с top модулем будет syscontrol,vhd - последний в порядке синтеза .vhdl файлов.

 

Т.к. top_cpm находится в файле top.v, процесс синтеза завершается ошибкой.

 

Symplify Pro 9.6 все это собирал нормально.

 

В doc по symplify кроме указания, что файл с top модулем должен быть последним в synthesis order, ничего не нашел.

 

Как победить?

 

Спасибо.

 

 

#Build: Synplify Pro I-2013.09-1 , Build 274R, Mar  1 2013
#install: C:\Synopsys\fpga_I2013091
#OS: Windows 7 6.1
#Hostname: OTD-1-11-10

#Implementation: cpm_top

$ Start of Compile
#Mon Jun 02 09:59:40 2014

Synopsys HDL Compiler, version comp201309rc, Build 006R, built Aug 28 2013
@N|Running in 32-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

Synopsys VHDL Compiler, version comp201309rc, Build 006R, built Aug 28 2013
@N|Running in 32-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@N: CD720 :"C:\Synopsys\fpga_I2013091\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\sys_control.vhd":4:7:4:17|Top entity is set to sys_control.
VHDL syntax check successful!
File C:\Synopsys\fpga_I2013091\bin64\c_vhdl.exe changed - recompiling

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 59MB peak: 60MB)

# Mon Jun 02 09:59:41 2014

###########################################################]
Synopsys Verilog Compiler, version comp201309rc, Build 006R, built Aug 28 2013
@N|Running in 32-bit mode
Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.

@I::"C:\Synopsys\fpga_I2013091\lib\xilinx\unisim_m10i.v"
@I::"C:\Synopsys\fpga_I2013091\lib\xilinx\unisim.v"
@I::"C:\Synopsys\fpga_I2013091\lib\vlog\umr_capim.v"
@I::"C:\Synopsys\fpga_I2013091\lib\vlog\scemi_objects.v"
@I::"C:\Synopsys\fpga_I2013091\lib\vlog\scemi_pipes.svh"
@I::"C:\Synopsys\fpga_I2013091\lib\vlog\hypermods.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\timescale.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_constants.v"
@I:"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_constants.v":"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_user_constants.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\bus_commands.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_async_reset_flop.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_async_reset_flop.v":72:12:72:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_async_reset_flop.v":74:12:74:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_cbe_en_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_cbe_en_crit.v":64:12:64:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_cbe_en_crit.v":66:12:66:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_conf_cyc_addr_dec.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_conf_cyc_addr_dec.v":64:12:64:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_conf_cyc_addr_dec.v":66:12:66:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_conf_space.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_conf_space.v":99:12:99:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_conf_space.v":101:12:101:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_cur_out_reg.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_cur_out_reg.v":59:12:59:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_cur_out_reg.v":61:12:61:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_delayed_sync.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_delayed_sync.v":77:12:77:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_delayed_sync.v":79:12:79:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_delayed_write_reg.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_delayed_write_reg.v":61:12:61:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_delayed_write_reg.v":63:12:63:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_en_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_en_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_en_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_load_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_load_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_frame_load_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_in_reg.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_in_reg.v":65:12:65:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_in_reg.v":67:12:67:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux.v":68:12:68:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux.v":70:12:70:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux_ad_en_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux_ad_en_crit.v":55:12:55:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux_ad_en_crit.v":57:12:57:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux_ad_load_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux_ad_load_crit.v":53:12:53:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_io_mux_ad_load_crit.v":55:12:55:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_irdy_out_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_irdy_out_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_irdy_out_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ad_en_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ad_en_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ad_en_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ad_load_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ad_load_crit.v":52:12:52:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ad_load_crit.v":54:12:54:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ch_state_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ch_state_crit.v":64:12:64:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_mas_ch_state_crit.v":66:12:66:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_master32_sm.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_master32_sm.v":64:12:64:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_master32_sm.v":66:12:66:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_master32_sm_if.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_master32_sm_if.v":74:12:74:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_master32_sm_if.v":76:12:76:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_out_reg.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_out_reg.v":61:12:61:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_out_reg.v":63:12:63:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_par_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_par_crit.v":67:12:67:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_par_crit.v":69:12:69:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_parity_check.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_parity_check.v":65:12:65:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_parity_check.v":67:12:67:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_decoder.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_decoder.v":61:12:61:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_decoder.v":63:12:63:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_tpram.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_tpram.v":101:12:101:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_tpram.v":103:12:103:23|Read directive translate_on 
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_tpram.v":437:12:437:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pci_tpram.v":461:12:461:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pcir_fifo_control.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pcir_fifo_control.v":90:12:90:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pcir_fifo_control.v":92:12:92:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pciw_fifo_control.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pciw_fifo_control.v":60:12:60:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pciw_fifo_control.v":62:12:62:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pciw_pcir_fifos.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pciw_pcir_fifos.v":99:12:99:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_pciw_pcir_fifos.v":101:12:101:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_perr_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_perr_crit.v":67:12:67:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_perr_crit.v":69:12:69:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_perr_en_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_perr_en_crit.v":67:12:67:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_perr_en_crit.v":69:12:69:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_rst_int.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_rst_int.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_rst_int.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_serr_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_serr_crit.v":67:12:67:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_serr_crit.v":69:12:69:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_serr_en_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_serr_en_crit.v":67:12:67:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_serr_en_crit.v":69:12:69:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_sync_module.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_sync_module.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_sync_module.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_synchronizer_flop.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_synchronizer_flop.v":70:12:70:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_synchronizer_flop.v":72:12:72:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target_unit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target_unit.v":104:12:104:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target_unit.v":106:12:106:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_clk_en.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_clk_en.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_clk_en.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_devs_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_devs_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_devs_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_interface.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_interface.v":87:12:87:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_interface.v":89:12:89:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_sm.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_sm.v":85:12:85:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_sm.v":87:12:87:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_stop_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_stop_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_stop_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_trdy_crit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_trdy_crit.v":62:12:62:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_target32_trdy_crit.v":64:12:64:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_addr_mux.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_addr_mux.v":64:12:64:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_addr_mux.v":66:12:66:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_decoder.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_decoder.v":63:12:63:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_decoder.v":65:12:65:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_master.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_master.v":91:11:91:23|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_master.v":93:11:93:22|Read directive translate_on 
@N: CG347 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_master.v":646:36:646:48|Read parallel_case directive 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_slave.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_slave.v":86:12:86:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_slave.v":88:12:88:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_slave_unit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_slave_unit.v":90:12:90:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_slave_unit.v":92:12:92:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_tpram.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_tpram.v":101:12:101:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_tpram.v":103:12:103:23|Read directive translate_on 
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_tpram.v":438:12:438:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wb_tpram.v":462:12:462:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbr_fifo_control.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbr_fifo_control.v":85:12:85:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbr_fifo_control.v":87:12:87:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_fifo_control.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_fifo_control.v":90:12:90:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_fifo_control.v":92:12:92:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_wbr_fifos.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_wbr_fifos.v":104:12:104:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_wbr_fifos.v":106:12:106:23|Read directive translate_on 
@N: CG347 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_wbr_fifos.v":352:46:352:58|Read parallel_case directive 
@N: CG347 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_wbw_wbr_fifos.v":396:45:396:57|Read parallel_case directive 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_bridge32.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_bridge32.v":113:12:113:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\pci_bridge32.v":115:12:115:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\top_pci.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\top_pci.v":84:12:84:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_1\top_pci.v":86:12:86:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\timescale.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_user_constants.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wbw_wbr_fifos.v"
@I:"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wbw_wbr_fifos.v":"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_constants.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wbw_wbr_fifos.v":104:12:104:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wbw_wbr_fifos.v":106:12:106:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wb_slave_unit.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wb_slave_unit.v":90:12:90:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_wb_slave_unit.v":92:12:92:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_conf_space.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_conf_space.v":99:12:99:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_conf_space.v":101:12:101:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_bridge32.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_bridge32.v":113:12:113:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\pci2_bridge32.v":115:12:115:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\ext_pci.v"
@N: CG334 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\ext_pci.v":84:12:84:24|Read directive translate_off 
@N: CG333 :"C:\Works\CP_M_fpga\cp_m_bagulnik\src\pci_2\ext_pci.v":86:12:86:23|Read directive translate_on 
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\buf32.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\wb_arbiter.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\wb_bus1.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\wb_bus0.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\timer.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\pci_arbiter.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\cpu_hub.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\bitmask_encoder.v"
@I::"C:\Works\CP_M_fpga\cp_m_bagulnik\src\sys_coontrol\top.v"
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 63MB peak: 65MB)

# Mon Jun 02 09:59:42 2014

###########################################################]
@E::Top level Module/Entity cpm_top, cannot be found in the design.
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Jun 02 09:59:42 2014

###########################################################]

[gosha 0]

Доп инфа:

 

Если файл проекта, который генерит AHDL попрапвить руками, удалив слово lib в указании исходника verilog, проект синтезируется.

Мне каждый раз руками править? Или есть какая-то галочка в опциях AHDL

 

Так не работает.

add_file -vhdl -lib work -folder {ide} "./ide/atahost_pio_tctrl.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/atahost_reg_buf.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/atahost_top.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/atahost_wb_slave.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/ro_cnt.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/ud_cnt.vhd"
add_file -verilog -lib work -folder {pci_1} "./pci_1/bus_commands.v"
add_file -verilog -lib work -folder {pci_1} "./pci_1/pci_async_reset_flop.v"
add_file -verilog -lib work -folder {pci_1} "./pci_1/pci_bridge32.v"
add_file -verilog -lib work -folder {pci_1} "./pci_1/pci_cbe_en_crit.v"

 

После редактирования руками проекта, автоматически с-генерированного AHDL:

Так собирается?

add_file -vhdl -lib work -folder {ide} "./ide/atahost_pio_tctrl.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/atahost_reg_buf.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/atahost_top.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/atahost_wb_slave.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/ro_cnt.vhd"
add_file -vhdl -lib work -folder {ide} "./ide/ud_cnt.vhd"
add_file -verilog -folder {pci_1} "./pci_1/bus_commands.v"
add_file -verilog -folder {pci_1} "./pci_1/pci_async_reset_flop.v"
add_file -verilog -folder {pci_1} "./pci_1/pci_bridge32.v"
add_file -verilog -folder {pci_1} "./pci_1/pci_cbe_en_crit.v"

 

Это BUG AHDL 9.3 ?