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WladimirK

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  1. Все, разобрался. Проблема была в подключении генераторов ко входам PHY. В моем случае надо использовать mgtrefclk0/1. Тогда ошибки уходят.
  2. Задача следующая. Надо подключить IP-Core Display Port Tx. Это IP подключается через Video PHY Controller к GTH (гигабитному приемопередатчику). Первым этапом я подключаю выходы FPGA (xczu4cg-fbvb900-1-e) к Video PHY Controller. Вот Block Disign: Затем выходы этого Block Design я просто передаю на выходы TX GTH. Вот код: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity top is Port ( DP_Dx_SEL: out std_logic; DP_AUX_SEL: out std_logic; DP_ENABLE: out std_logic; --DP TX OUT DP_MGT_TX_P: out std_logic_vector(3 downto 0); DP_MGT_TX_N: out std_logic_vector(3 downto 0)); end top; ----------------------------------------------------------------------------- ----------------------------------------------------------------------------- architecture Behavioral of top is signal clk100MHz: std_logic; signal phy_txp_out: std_logic_vector(3 downto 0); signal phy_txn_out: std_logic_vector(3 downto 0); signal ibuf_ds_p_0: std_logic; signal ibuf_ds_n_0: std_logic; signal ibuf_ds_p_1: std_logic; signal ibuf_ds_n_1: std_logic; ----------------------------------------------------------------------------- begin ----------------------------------------------------------------------------- --DP control initialisation DP_Dx_SEL<= '0'; DP_AUX_SEL<= '0'; DP_ENABLE<= '1'; DP_MGT_TX_P<= phy_txp_out; DP_MGT_TX_n<= phy_txn_out; --ZYNQ Block Design ZYNQ_VIDEO_BD:entity work.bd port map( clk100MHz=> clk100MHz, phy_txp_out=> phy_txp_out, phy_txn_out=> phy_txn_out, ibuf_ds_p_0=> ibuf_ds_p_0, ibuf_ds_n_0=> ibuf_ds_n_0, ibuf_ds_p_1=> ibuf_ds_p_1, ibuf_ds_n_1=> ibuf_ds_n_1 ); end Behavioral; Но после сборки проекта, на этапе Generate Bitstream, выскакиет ошибка: [DRC NSTD-1] Unspecified I/O Standard: 8 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DP_MGT_TX_N[3:0], and DP_MGT_TX_P[3:0]. [DRC UCIO-1] Unconstrained Logical Port: 8 out of 11 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DP_MGT_TX_N[3:0], and DP_MGT_TX_P[3:0]. Может кто подключал эту штуку и подскажет куда копать!? Что я упускаю?