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An Altera device family designed as a cost-effective solution for data path applications. The Cyclone III device architecture supports M9K memory blocks to implement single-port, dual-port, and true dual-port memory, and high-speed interfaces to external memory devices such as single data rate (SDR) SDRAM, double data rate (DDR) SDRAM, double data rate II (DDR-II) SDRAM and quad data rate II (QDR-II) SRAM. Cyclone III devices also contain embedded multiplier blocks that enable efficient implementation of high-performance filters and multipliers.
Cyclone III devices provide up to four PLLs per device, which provide advanced multiplication, programmable duty cycle, phase shifting, programmable bandwidth, manual clock switchover, clock outputs driving all networks, and normal and zero delay buffer modes. Cyclone III devices also provide up to 20 global clock lines that drive the global clock network throughout the entire device.
Cyclone III devices support numerous single-ended and differential I/O standards, including 1.2V CMOS, 1.5V CMOS, 1.5 V HSTL Class I & II, 1.8V CMOS, 2.5V CMOS, 2.5 V SSTL Class I & II, 3V CMOS, 3V LVTTL, 3V PCI/PCI-X, Differential HSTL-12 Class I & II, Differential HSTL-15 Class I & II, Differential HSTL-18 Class I & II, Differential SSTL-2 Class I & II, Differential SSTL-18 Class I & II, LVPECL (only on GCLK locations), HSTL-12 Class I & II, HSTL-15 Class I & II, HSTL-18 Class I & II, LVCMOS, LVDS, LVTTL, mini-LVDS (output only), PPDS (output only, RSDS (output only), SSTL-2 Class I & II, and SSTL-18 Class I & II. Dual-purpose clock (DPCLK) pins are used for delayed clocking for DQS and for high-fanout PCI signals. Differential HSTL and SSTL outputs are only supported on PLLCLKOUTs. Differential HSTL and SSTL inputs use VREF input buffers and are supported only on clock inputs.
The memory blocks of a Cyclone III device can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port RAM single-port RAM; ROM; FIFO buffers; and shift registers. Also, clock delay can be controlled dynamically in Cyclone III devices.
Cyclone III devices have 10 or 20 global clock networks, which can be driven by dedicated clock input pins, PLL counter outputs, dual purpose clock input pins, or non-peripheral logic.
You can use device migration to transfer a design between Cyclone III devices with equivalent pin-outs, while maintaining the same board layout and pin assignments.
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