Nikolas72_91 1 December 14, 2025 Posted December 14, 2025 · Report post Здравствуйте, написал цифровой предсказатель сигнала выдающий сигнал на выходе опережающий входной, но скорость проекта не сильно высокая выше 50 МГц тактовой частоты не получается разогнать на EPM240 из за задержек в плис, пробовал компилировать в GOWIN IDE пишет допустимая частота 80 МГц на чипе GW1N-LV9. Констрейны настраивал. Как оптимизировать проект, чтобы разогнать его на частоту выше 100 МГц для уменьшения джиттера. Проект нужен, чтобы компенсировать задержки распространения сигнала всей схемы для резонансного инвертора. Часто кода взял с хабра https://habr.com/ru/articles/273851/ Констрейны create_clock -name {CLK_IN} -period 100MHz [get_ports {CLK_IN}] create_clock -name {zcd_input} -period 1MHz [get_ports {zcd_input}] Исходный код library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity Driver is generic ( N : integer :=2048; --Разрядность счетчика FREQ_CLK : integer := 50; -- CLK input 50 MHz phase_shift : integer := 1000 -- смещение опережения фазы в нсек ); Port ( zcd_input : in std_logic; -- ZCD Feedback off_signal : in std_logic; -- OFF signal input CLK_IN : in std_logic; -- CLK input 50 MHz DRIVER_OUT : out std_logic -- signal output ); end Driver; architecture Behavioral of Driver is type state_type is (set_level, wait_high_low, wait_low_high); -- описание машины состояний signal current_stage : state_type; signal counter_shift : integer range 0 to N := 0; -- внутренний счетчик signal r_count : integer range 0 to N := 0; signal len_pulse : integer range 0 to N := 0; signal len_pulse_last : integer range 0 to N := 0; signal TICKS_PHASE_SHIFT : integer range 0 to N := 0; signal shift_reg : std_logic_vector(2 downto 0) := (others=>'0'); signal PERIOD_CLK : integer range 0 to 127 := 0; signal r_count_ena : std_logic; signal all_edge : std_logic; signal zcd_input_out : std_logic; signal switch_disable : std_logic; signal switch_delay : std_logic; begin --Формулы для расчета констант из значений частот --============================================== PERIOD_CLK <= (1000000000/(FREQ_CLK*1000000)); -- расчет периода тактовой частоты TICKS_PHASE_SHIFT <= ((phase_shift/PERIOD_CLK) - 1); --============================================== -- Генератор фазового сдвига --============================================== shift_fsm : process (CLK_IN, zcd_input, TICKS_PHASE_SHIFT, switch_disable, switch_delay) begin if TICKS_PHASE_SHIFT = 0 or switch_disable = '1' or switch_delay = '0' then zcd_input_out <= zcd_input; counter_shift <= 0; current_stage <= set_level; elsif rising_edge(CLK_IN) then case current_stage is when set_level => if counter_shift = len_pulse - TICKS_PHASE_SHIFT then -- после выставленной задержки, подаём на выход 0 или 1 if zcd_input = '1' then zcd_input_out <= '0'; current_stage <= wait_high_low; else zcd_input_out <= '1'; current_stage <= wait_low_high; end if; counter_shift <= 0; elsif counter_shift < len_pulse - TICKS_PHASE_SHIFT then counter_shift <= counter_shift + 1; current_stage <= set_level; end if; when wait_high_low => -- ждем переключения 1 на 0 и возвращаемся в set_level if zcd_input = '1' then current_stage <= wait_high_low; else current_stage <= set_level; end if; when wait_low_high => -- ждем переключения 0 на 1 и возвращаемся в set_level if zcd_input = '0' then current_stage <= wait_low_high; else current_stage <= set_level; end if; when others => current_stage <= set_level; end case; end if; end process shift_fsm; --============================================== -- Детектор фронтов --============================================== edge_detector : process(CLK_IN) begin if(rising_edge(CLK_IN)) then shift_reg <= shift_reg(1 downto 0) & zcd_input; -- _________|-------|________ end if; end process edge_detector; all_edge <= shift_reg(1) xor shift_reg(0); -- __________п______п________ выдает короткий импульс по возрастающему и спадающему фронту входного сигнала --============================================== -- Измеритель длительности полупериодов --============================================== pulse_counter : process(CLK_IN, off_signal) begin if(off_signal='0') then -- обнуление всех сигналов и счетчиков при 0 reset асинхронно r_count_ena <= '0'; r_count <= 0; len_pulse <= 0; len_pulse_last <= 0; elsif(rising_edge(CLK_IN)) then -- по возрастающему фронту clk и детектору возрастающего фронта устанавливаюся сигналы в разрешения работы счетчика и вывод данных в регистр хранения if(all_edge='1') then r_count_ena <= '1'; -- установка сигнала разрешения счета r_count <= 0; -- сброс счетчика по детекору фронтов 0 len_pulse <= r_count; len_pulse_last <= len_pulse; elsif(r_count_ena='1') then r_count <= r_count + 1; -- если разрешающий сигнал 1 то начинается счет end if; end if; end process pulse_counter; --============================================== --Сравнение 2х полупериодов для сброса сдвига если частота понижается. --============================================== compare2 : process(CLK_IN, off_signal, switch_delay) begin if(off_signal = '0' and switch_delay = '0' ) then switch_disable <= '0'; elsif(rising_edge(CLK_IN)) then if (len_pulse < len_pulse_last - TICKS_PHASE_SHIFT) then switch_disable <= '1'; else switch_disable <= '0'; end if; end if; end process compare2; --============================================== -- Задержка разрешения фазового сдвига для стабилизации сигнала --============================================== switch_delay_pr : process(CLK_IN, off_signal) begin if (off_signal = '0') then switch_delay <= '0'; elsif (rising_edge(CLK_IN)) then if ((len_pulse > TICKS_PHASE_SHIFT) and (len_pulse_last > TICKS_PHASE_SHIFT)) then switch_delay <= '1'; else switch_delay <= '0'; end if; end if; end process switch_delay_pr ; --============================================== -- Вывод сигналов с плис на драйвера --============================================== DRIVER_OUT <= zcd_input_out; --============================================== end Behavioral; Quote Share this post Link to post Share on other sites More sharing options...
fpga_dev 11 December 14, 2025 Posted December 14, 2025 · Report post Детально не вникал но несколько соображений: Самая длинная цепочка у вас Quote if (len_pulse < len_pulse_last - TICKS_PHASE_SHIFT) then что представляет из себя 2 12и битных сумматора один за другим. Если в плис нет логики быстрого переноса, то это может подтормаживать (хотя 50Mhz как-то маловато). Во первых нужно внимательно прочитать timing report и убедиться где конкретно проблема. Далее, вы можете вычитание len_pulse - TICKS_PHASE_SHIFT произвести заранее, например в тот момент когда вы присваиваете len_pulse <= r_count; Ну и по мелочи: N лучше сделать 2047 а не 2048, сэкономит вам один разряд. Или задавать диапазон 0 to N-1. Для констант типа TICKS_PHASE_SHIFT лучше использовать constant а не signal, в теории компилятор и так должен сделать все правильно но лучше его не искушать 😉 Асинхронные входы (zcd_filter и off_signal) надо как минимум регистрировать в IOB (или как в вашей плис называются IO регистры) а по хорошему ставить фильтр одиночных глюков. И тогда кстати можно будет использовать синхронный ресет. Quote Share this post Link to post Share on other sites More sharing options...
Nikolas72_91 1 December 14, 2025 Posted December 14, 2025 · Report post 8 часов назад, Nikolas72_91 сказал: Здравствуйте, написал цифровой предсказатель сигнала выдающий сигнал на выходе опережающий входной, но скорость проекта не сильно высокая выше 50 МГц тактовой частоты не получается разогнать на EPM240 из за задержек в плис, пробовал компилировать в GOWIN IDE пишет допустимая частота 80 МГц на чипе GW1N-LV9. Констрейны настраивал. Как оптимизировать проект, чтобы разогнать его на частоту выше 100 МГц для уменьшения джиттера. Проект нужен, чтобы компенсировать задержки распространения сигнала всей схемы для резонансного инвертора. Часто кода взял с хабра https://habr.com/ru/articles/273851/ Констрейны create_clock -name {CLK_IN} -period 100MHz [get_ports {CLK_IN}] create_clock -name {zcd_input} -period 1MHz [get_ports {zcd_input}] Исходный код library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity Driver is generic ( N : integer :=2048; --Разрядность счетчика FREQ_CLK : integer := 50; -- CLK input 50 MHz phase_shift : integer := 1000 -- смещение опережения фазы в нсек ); Port ( zcd_input : in std_logic; -- ZCD Feedback off_signal : in std_logic; -- OFF signal input CLK_IN : in std_logic; -- CLK input 50 MHz DRIVER_OUT : out std_logic -- signal output ); end Driver; architecture Behavioral of Driver is type state_type is (set_level, wait_high_low, wait_low_high); -- описание машины состояний signal current_stage : state_type; signal counter_shift : integer range 0 to N := 0; -- внутренний счетчик signal r_count : integer range 0 to N := 0; signal len_pulse : integer range 0 to N := 0; signal len_pulse_last : integer range 0 to N := 0; signal TICKS_PHASE_SHIFT : integer range 0 to N := 0; signal shift_reg : std_logic_vector(2 downto 0) := (others=>'0'); signal PERIOD_CLK : integer range 0 to 127 := 0; signal r_count_ena : std_logic; signal all_edge : std_logic; signal zcd_input_out : std_logic; signal switch_disable : std_logic; signal switch_delay : std_logic; begin --Формулы для расчета констант из значений частот --============================================== PERIOD_CLK <= (1000000000/(FREQ_CLK*1000000)); -- расчет периода тактовой частоты TICKS_PHASE_SHIFT <= ((phase_shift/PERIOD_CLK) - 1); --============================================== -- Генератор фазового сдвига --============================================== shift_fsm : process (CLK_IN, zcd_input, TICKS_PHASE_SHIFT, switch_disable, switch_delay) begin if TICKS_PHASE_SHIFT = 0 or switch_disable = '1' or switch_delay = '0' then zcd_input_out <= zcd_input; counter_shift <= 0; current_stage <= set_level; elsif rising_edge(CLK_IN) then case current_stage is when set_level => if counter_shift = len_pulse - TICKS_PHASE_SHIFT then -- после выставленной задержки, подаём на выход 0 или 1 if zcd_input = '1' then zcd_input_out <= '0'; current_stage <= wait_high_low; else zcd_input_out <= '1'; current_stage <= wait_low_high; end if; counter_shift <= 0; elsif counter_shift < len_pulse - TICKS_PHASE_SHIFT then counter_shift <= counter_shift + 1; current_stage <= set_level; end if; when wait_high_low => -- ждем переключения 1 на 0 и возвращаемся в set_level if zcd_input = '1' then current_stage <= wait_high_low; else current_stage <= set_level; end if; when wait_low_high => -- ждем переключения 0 на 1 и возвращаемся в set_level if zcd_input = '0' then current_stage <= wait_low_high; else current_stage <= set_level; end if; when others => current_stage <= set_level; end case; end if; end process shift_fsm; --============================================== -- Детектор фронтов --============================================== edge_detector : process(CLK_IN) begin if(rising_edge(CLK_IN)) then shift_reg <= shift_reg(1 downto 0) & zcd_input; -- _________|-------|________ end if; end process edge_detector; all_edge <= shift_reg(1) xor shift_reg(0); -- __________п______п________ выдает короткий импульс по возрастающему и спадающему фронту входного сигнала --============================================== -- Измеритель длительности полупериодов --============================================== pulse_counter : process(CLK_IN, off_signal) begin if(off_signal='0') then -- обнуление всех сигналов и счетчиков при 0 reset асинхронно r_count_ena <= '0'; r_count <= 0; len_pulse <= 0; len_pulse_last <= 0; elsif(rising_edge(CLK_IN)) then -- по возрастающему фронту clk и детектору возрастающего фронта устанавливаюся сигналы в разрешения работы счетчика и вывод данных в регистр хранения if(all_edge='1') then r_count_ena <= '1'; -- установка сигнала разрешения счета r_count <= 0; -- сброс счетчика по детекору фронтов 0 len_pulse <= r_count; len_pulse_last <= len_pulse; elsif(r_count_ena='1') then r_count <= r_count + 1; -- если разрешающий сигнал 1 то начинается счет end if; end if; end process pulse_counter; --============================================== --Сравнение 2х полупериодов для сброса сдвига если частота понижается. --============================================== compare2 : process(CLK_IN, off_signal, switch_delay) begin if(off_signal = '0' and switch_delay = '0' ) then switch_disable <= '0'; elsif(rising_edge(CLK_IN)) then if (len_pulse < len_pulse_last - TICKS_PHASE_SHIFT) then switch_disable <= '1'; else switch_disable <= '0'; end if; end if; end process compare2; --============================================== -- Задержка разрешения фазового сдвига для стабилизации сигнала --============================================== switch_delay_pr : process(CLK_IN, off_signal) begin if (off_signal = '0') then switch_delay <= '0'; elsif (rising_edge(CLK_IN)) then if ((len_pulse > TICKS_PHASE_SHIFT) and (len_pulse_last > TICKS_PHASE_SHIFT)) then switch_delay <= '1'; else switch_delay <= '0'; end if; end if; end process switch_delay_pr ; --============================================== -- Вывод сигналов с плис на драйвера --============================================== DRIVER_OUT <= zcd_input_out; --============================================== end Behavioral; Здравствуйте, спасибо за комментарии некоторые внес в код спасибо. if (len_pulse < len_pulse_last - TICKS_PHASE_SHIFT) then это была цепочка сравнения переменных Вот длинная цепочка была len_pulse <= r_count; len_pulse_last <= len_pulse; Спасибо, что заметили, да забыл 1 вычесть N лучше сделать 2047 а не 2048. Переписал по другому до этого писало fmax 70 МГц на epm240T100C5N теперь 100.58 МГц но хотелось бы еще выше хотя бы 150-200 МГц желательно. На GW1N-LV9 пишет частоту 98 МГц максимум, что как то мало для более современной fpga Может будут идеи как еще улучшить тайминги приложил library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity Driver is generic ( N : integer :=2047; --Разрядность счетчика FREQ_CLK : integer := 50; -- CLK input 50 MHz phase_shift : integer := 600 -- смещение опережения фазы в нсек ); Port ( zcd_input : in std_logic; -- ZCD Feedback off_signal : in std_logic; -- OFF signal input CLK_IN : in std_logic; -- CLK input 50 MHz DRIVER_OUT : out std_logic -- signal output ); end Driver; architecture Behavioral of Driver is type state_type is (set_level, wait_high_low, wait_low_high); -- описание машины состояний signal current_stage : state_type; signal counter_shift : integer range 0 to N := 0; -- внутренний счетчик signal r_count : integer range 0 to N := 0; signal len_pulse : integer range - N to N := 0; signal TICKS_PHASE_SHIFT : integer range 0 to N := 0; signal shift_reg : std_logic_vector(2 downto 0) := (others=>'0'); signal PERIOD_CLK : integer range 0 to 127 := 0; signal r_count_ena : std_logic; signal all_edge : std_logic; signal zcd_input_out : std_logic; signal switch_disable : std_logic; signal switch_delay : std_logic; begin --Формулы для расчета констант из значений частот --============================================== PERIOD_CLK <= (1000000000/(FREQ_CLK*1000000)); -- расчет периода тактовой частоты TICKS_PHASE_SHIFT <= ((phase_shift/PERIOD_CLK) - 1); --============================================== -- Генератор фазового сдвига --============================================== shift_fsm : process (CLK_IN, zcd_input, TICKS_PHASE_SHIFT, switch_disable, switch_delay) begin if TICKS_PHASE_SHIFT = 0 or switch_disable = '1' or switch_delay = '0' then zcd_input_out <= zcd_input; counter_shift <= 0; current_stage <= set_level; elsif rising_edge(CLK_IN) then case current_stage is when set_level => if counter_shift = len_pulse then -- после выставленной задержки, подаём на выход 0 или 1 if zcd_input = '1' then zcd_input_out <= '0'; current_stage <= wait_high_low; else zcd_input_out <= '1'; current_stage <= wait_low_high; end if; counter_shift <= 0; elsif counter_shift < len_pulse then counter_shift <= counter_shift + 1; current_stage <= set_level; end if; when wait_high_low => -- ждем переключения 1 на 0 и возвращаемся в set_level if zcd_input = '1' then current_stage <= wait_high_low; else current_stage <= set_level; end if; when wait_low_high => -- ждем переключения 0 на 1 и возвращаемся в set_level if zcd_input = '0' then current_stage <= wait_low_high; else current_stage <= set_level; end if; when others => current_stage <= set_level; end case; end if; end process shift_fsm; --============================================== -- Детектор фронтов --============================================== edge_detector : process(CLK_IN) begin if(rising_edge(CLK_IN)) then shift_reg <= shift_reg(1 downto 0) & zcd_input; -- _________|-------|________ end if; all_edge <= shift_reg(1) xor shift_reg(0); -- __________п______п________ выдает короткий импульс по возрастающему и спадающему фронту входного сигнала end process edge_detector; --============================================== -- Измеритель длительности полупериодов --============================================== pulse_counter : process(CLK_IN, off_signal) begin if(off_signal='0') then -- обнуление всех сигналов и счетчиков при 0 reset асинхронно r_count_ena <= '0'; r_count <= 0; len_pulse <= 0; elsif(rising_edge(CLK_IN)) then -- по возрастающему фронту clk и детектору возрастающего фронта устанавливаюся сигналы в разрешения работы счетчика и вывод данных в регистр хранения if(all_edge='1') then r_count_ena <= '1'; -- установка сигнала разрешения счета r_count <= 0; -- сброс счетчика по детекору фронтов 0 len_pulse <= r_count - TICKS_PHASE_SHIFT; elsif(r_count_ena='1') then r_count <= r_count + 1; -- если разрешающий сигнал 1 то начинается счет end if; end if; end process pulse_counter; --============================================== --Сравнение 2х полупериодов для сброса сдвига если частота понижается. --============================================== compare2 : process(all_edge, off_signal, switch_delay) begin if(off_signal = '0' and switch_delay = '0' ) then switch_disable <= '0'; elsif(rising_edge(all_edge)) then if (r_count < len_pulse ) then switch_disable <= '1'; else switch_disable <= '0'; end if; end if; end process compare2; --============================================== -- Задержка разрешения фазового сдвига для стабилизации сигнала --============================================== switch_delay_pr : process(CLK_IN, off_signal) begin if (off_signal = '0') then switch_delay <= '0'; elsif (rising_edge(CLK_IN)) then if ((len_pulse > TICKS_PHASE_SHIFT)) then switch_delay <= '1'; else switch_delay <= '0'; end if; end if; end process switch_delay_pr ; --============================================== -- Вывод сигналов с плис на драйвера --============================================== DRIVER_OUT <= zcd_input_out; --============================================== end Behavioral; Report all core timing вот такой теперь slack. from node. to node launch clk latch clk. relationship clk skew data delay № 0.058 len_pulse[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.609 1 0.058 len_pulse[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.609 2 0.058 len_pulse[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.609 3 0.058 len_pulse[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.609 4 0.058 len_pulse[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.609 5 0.086 len_pulse[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.581 6 0.086 len_pulse[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.581 7 0.086 len_pulse[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.581 8 0.086 len_pulse[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.581 9 0.086 len_pulse[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.581 10 0.167 len_pulse[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.500 11 0.167 len_pulse[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.500 12 0.167 len_pulse[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.500 13 0.167 len_pulse[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.500 14 0.167 len_pulse[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.500 15 0.204 counter_shift[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.463 16 0.204 counter_shift[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.463 17 0.204 counter_shift[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.463 18 0.204 counter_shift[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.463 19 0.204 counter_shift[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.463 20 0.209 len_pulse[4] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.458 21 0.209 len_pulse[4] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.458 22 0.209 len_pulse[4] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.458 23 0.209 len_pulse[4] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.458 24 0.209 len_pulse[4] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.458 25 0.216 len_pulse[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.451 26 0.216 len_pulse[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.451 27 0.216 len_pulse[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.451 28 0.216 len_pulse[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.451 29 0.216 len_pulse[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.451 30 0.245 counter_shift[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.422 31 0.245 counter_shift[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.422 32 0.245 counter_shift[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.422 33 0.245 counter_shift[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.422 34 0.245 counter_shift[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.422 35 0.308 counter_shift[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.359 36 0.308 counter_shift[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.359 37 0.308 counter_shift[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.359 38 0.308 counter_shift[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.359 39 0.308 counter_shift[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.359 40 0.352 len_pulse[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.315 41 0.352 len_pulse[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.315 42 0.352 len_pulse[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.315 43 0.352 len_pulse[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.315 44 0.352 len_pulse[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.315 45 0.360 counter_shift[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.307 46 0.360 counter_shift[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.307 47 0.360 counter_shift[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.307 48 0.360 counter_shift[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.307 49 0.360 counter_shift[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.307 50 0.389 len_pulse[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.278 51 0.389 len_pulse[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.278 52 0.389 len_pulse[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.278 53 0.389 len_pulse[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.278 54 0.389 len_pulse[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.278 55 0.395 counter_shift[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.272 56 0.395 counter_shift[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.272 57 0.395 counter_shift[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.272 58 0.395 counter_shift[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.272 59 0.395 counter_shift[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.272 60 0.424 counter_shift[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.243 61 0.424 counter_shift[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.243 62 0.424 counter_shift[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.243 63 0.424 counter_shift[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.243 64 0.424 counter_shift[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.243 65 0.441 len_pulse[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.226 66 0.441 len_pulse[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.226 67 0.441 len_pulse[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.226 68 0.441 len_pulse[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.226 69 0.441 len_pulse[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.226 70 0.441 len_pulse[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.226 71 0.469 len_pulse[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.198 72 0.469 len_pulse[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.198 73 0.469 len_pulse[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.198 74 0.469 len_pulse[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.198 75 0.469 len_pulse[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.198 76 0.469 len_pulse[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.198 77 0.485 counter_shift[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.182 78 0.485 counter_shift[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.182 79 0.485 counter_shift[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.182 80 0.485 counter_shift[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.182 81 0.485 counter_shift[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.182 82 0.512 len_pulse[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.155 83 0.512 len_pulse[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.155 84 0.512 len_pulse[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.155 85 0.512 len_pulse[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.155 86 0.512 len_pulse[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.155 87 0.515 counter_shift[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.152 88 0.515 counter_shift[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.152 89 0.515 counter_shift[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.152 90 0.515 counter_shift[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.152 91 0.515 counter_shift[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.152 92 0.535 counter_shift[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.132 93 0.535 counter_shift[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.132 94 0.535 counter_shift[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.132 95 0.535 counter_shift[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.132 96 0.535 counter_shift[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.132 97 0.550 len_pulse[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.117 98 0.550 len_pulse[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.117 99 0.550 len_pulse[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.117 100 0.550 len_pulse[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.117 101 0.550 len_pulse[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.117 102 0.550 len_pulse[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.117 103 0.551 len_pulse[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.116 104 0.551 len_pulse[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.116 105 0.551 len_pulse[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.116 106 0.551 len_pulse[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.116 107 0.551 len_pulse[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.116 108 0.552 len_pulse[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.115 109 0.552 len_pulse[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.115 110 0.552 len_pulse[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.115 111 0.552 len_pulse[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.115 112 0.552 len_pulse[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.115 113 0.564 len_pulse[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.103 114 0.564 len_pulse[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.103 115 0.564 len_pulse[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.103 116 0.564 len_pulse[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.103 117 0.564 len_pulse[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.103 118 0.587 counter_shift[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.080 119 0.587 counter_shift[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.080 120 0.587 counter_shift[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.080 121 0.587 counter_shift[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.080 122 0.587 counter_shift[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.080 123 0.587 counter_shift[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.080 124 0.592 len_pulse[4] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.075 125 0.592 len_pulse[4] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.075 126 0.592 len_pulse[4] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.075 127 0.592 len_pulse[4] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.075 128 0.592 len_pulse[4] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.075 129 0.592 len_pulse[4] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.075 130 0.599 len_pulse[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.068 131 0.599 len_pulse[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.068 132 0.599 len_pulse[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.068 133 0.599 len_pulse[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.068 134 0.599 len_pulse[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.068 135 0.599 len_pulse[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.068 136 0.615 counter_shift[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.052 137 0.615 counter_shift[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.052 138 0.615 counter_shift[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.052 139 0.615 counter_shift[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.052 140 0.615 counter_shift[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.052 141 0.628 counter_shift[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 9.039 142 0.628 counter_shift[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 9.039 143 0.628 counter_shift[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 9.039 144 0.628 counter_shift[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 9.039 145 0.628 counter_shift[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 9.039 146 0.628 counter_shift[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 9.039 147 0.653 counter_shift[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.014 148 0.653 counter_shift[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.014 149 0.653 counter_shift[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.014 150 0.653 counter_shift[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.014 151 0.653 counter_shift[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.014 152 0.666 len_pulse[9] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 9.001 153 0.666 len_pulse[9] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 9.001 154 0.666 len_pulse[9] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 9.001 155 0.666 len_pulse[9] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 9.001 156 0.666 len_pulse[9] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 9.001 157 0.673 len_pulse[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.994 158 0.673 len_pulse[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.994 159 0.673 len_pulse[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.994 160 0.673 len_pulse[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.994 161 0.673 len_pulse[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.994 162 0.690 len_pulse[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.977 163 0.690 len_pulse[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.977 164 0.690 len_pulse[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.977 165 0.690 len_pulse[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.977 166 0.690 len_pulse[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.977 167 0.691 counter_shift[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.976 168 0.691 counter_shift[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.976 169 0.691 counter_shift[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.976 170 0.691 counter_shift[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.976 171 0.691 counter_shift[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.976 172 0.691 counter_shift[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.976 173 0.735 len_pulse[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.932 174 0.735 len_pulse[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.932 175 0.735 len_pulse[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.932 176 0.735 len_pulse[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.932 177 0.735 len_pulse[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.932 178 0.735 len_pulse[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.932 179 0.743 counter_shift[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.924 180 0.743 counter_shift[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.924 181 0.743 counter_shift[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.924 182 0.743 counter_shift[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.924 183 0.743 counter_shift[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.924 184 0.743 counter_shift[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.924 185 0.766 len_pulse[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.901 186 0.766 len_pulse[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.901 187 0.766 len_pulse[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.901 188 0.766 len_pulse[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.901 189 0.766 len_pulse[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.901 190 0.772 len_pulse[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.895 191 0.772 len_pulse[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.895 192 0.772 len_pulse[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.895 193 0.772 len_pulse[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.895 194 0.772 len_pulse[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.895 195 0.772 len_pulse[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.895 196 0.778 counter_shift[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.889 197 0.778 counter_shift[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.889 198 0.778 counter_shift[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.889 199 0.778 counter_shift[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.889 200 0.778 counter_shift[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.889 201 0.778 counter_shift[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.889 202 0.807 counter_shift[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.860 203 0.807 counter_shift[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.860 204 0.807 counter_shift[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.860 205 0.807 counter_shift[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.860 206 0.807 counter_shift[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.860 207 0.807 counter_shift[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.860 208 0.811 counter_shift[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.856 209 0.811 counter_shift[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.856 210 0.811 counter_shift[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.856 211 0.811 counter_shift[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.856 212 0.811 counter_shift[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.856 213 0.812 len_pulse[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.855 214 0.812 len_pulse[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.855 215 0.812 len_pulse[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.855 216 0.812 len_pulse[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.855 217 0.812 len_pulse[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.855 218 0.827 counter_shift[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.840 219 0.827 counter_shift[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.840 220 0.827 counter_shift[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.840 221 0.827 counter_shift[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.840 222 0.827 counter_shift[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.840 223 0.837 counter_shift[4] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.830 224 0.837 counter_shift[4] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.830 225 0.837 counter_shift[4] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.830 226 0.837 counter_shift[4] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.830 227 0.837 counter_shift[4] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.830 228 0.862 len_pulse[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.805 229 0.862 len_pulse[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.805 230 0.862 len_pulse[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.805 231 0.862 len_pulse[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.805 232 0.862 len_pulse[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.805 233 0.862 len_pulse[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.805 234 0.862 len_pulse[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.805 235 0.862 len_pulse[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.805 236 0.862 len_pulse[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.805 237 0.862 len_pulse[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.805 238 0.865 len_pulse[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.802 239 0.865 len_pulse[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.802 240 0.865 len_pulse[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.802 241 0.865 len_pulse[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.802 242 0.865 len_pulse[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.802 243 0.868 counter_shift[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.799 244 0.868 counter_shift[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.799 245 0.868 counter_shift[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.799 246 0.868 counter_shift[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.799 247 0.868 counter_shift[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.799 248 0.868 counter_shift[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.799 249 0.888 len_pulse[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.779 250 0.888 len_pulse[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.779 251 0.888 len_pulse[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.779 252 0.888 len_pulse[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.779 253 0.888 len_pulse[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.779 254 0.895 len_pulse[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.772 255 0.895 len_pulse[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.772 256 0.895 len_pulse[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.772 257 0.895 len_pulse[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.772 258 0.895 len_pulse[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.772 259 0.895 len_pulse[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.772 260 0.898 counter_shift[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.769 261 0.898 counter_shift[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.769 262 0.898 counter_shift[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.769 263 0.898 counter_shift[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.769 264 0.898 counter_shift[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.769 265 0.898 counter_shift[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.769 266 0.918 counter_shift[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.749 267 0.918 counter_shift[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.749 268 0.918 counter_shift[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.749 269 0.918 counter_shift[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.749 270 0.918 counter_shift[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.749 271 0.918 counter_shift[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.749 272 0.934 len_pulse[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.733 273 0.934 len_pulse[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.733 274 0.934 len_pulse[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.733 275 0.934 len_pulse[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.733 276 0.934 len_pulse[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.733 277 0.934 len_pulse[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.733 278 0.935 len_pulse[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.732 279 0.935 len_pulse[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.732 280 0.935 len_pulse[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.732 281 0.935 len_pulse[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.732 282 0.935 len_pulse[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.732 283 0.935 len_pulse[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.732 284 0.947 len_pulse[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.720 285 0.947 len_pulse[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.720 286 0.947 len_pulse[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.720 287 0.947 len_pulse[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.720 288 0.947 len_pulse[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.720 289 0.947 len_pulse[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.720 290 0.960 counter_shift[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.707 291 0.960 counter_shift[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.707 292 0.960 counter_shift[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.707 293 0.960 counter_shift[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.707 294 0.960 counter_shift[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.707 295 0.974 counter_shift[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.693 296 0.974 counter_shift[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.693 297 0.974 counter_shift[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.693 298 0.974 counter_shift[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.693 299 0.974 counter_shift[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.693 300 0.980 counter_shift[10] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.687 301 0.980 counter_shift[10] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.687 302 0.980 counter_shift[10] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.687 303 0.980 counter_shift[10] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.687 304 0.980 counter_shift[10] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.687 305 0.988 len_pulse[9] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.679 306 0.988 len_pulse[9] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.679 307 0.988 len_pulse[9] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.679 308 0.988 len_pulse[9] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.679 309 0.988 len_pulse[9] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.679 310 0.998 counter_shift[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.669 311 0.998 counter_shift[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.669 312 0.998 counter_shift[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.669 313 0.998 counter_shift[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.669 314 0.998 counter_shift[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.669 315 0.998 counter_shift[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.669 316 1.012 len_pulse[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.655 317 1.012 len_pulse[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.655 318 1.012 len_pulse[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.655 319 1.012 len_pulse[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.655 320 1.012 len_pulse[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.655 321 1.019 len_pulse[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.648 322 1.019 len_pulse[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.648 323 1.019 len_pulse[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.648 324 1.019 len_pulse[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.648 325 1.019 len_pulse[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.648 326 1.036 counter_shift[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.631 327 1.036 counter_shift[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.631 328 1.036 counter_shift[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.631 329 1.036 counter_shift[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.631 330 1.036 counter_shift[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.631 331 1.036 counter_shift[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.631 332 1.049 len_pulse[9] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.618 333 1.049 len_pulse[9] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.618 334 1.049 len_pulse[9] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.618 335 1.049 len_pulse[9] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.618 336 1.049 len_pulse[9] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.618 337 1.049 len_pulse[9] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.618 338 1.056 len_pulse[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.611 339 1.056 len_pulse[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.611 340 1.056 len_pulse[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.611 341 1.056 len_pulse[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.611 342 1.056 len_pulse[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.611 343 1.056 len_pulse[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.611 344 1.067 len_pulse[10] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.600 345 1.067 len_pulse[10] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.600 346 1.067 len_pulse[10] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.600 347 1.067 len_pulse[10] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.600 348 1.067 len_pulse[10] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.600 349 1.073 len_pulse[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.594 350 1.073 len_pulse[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.594 351 1.073 len_pulse[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.594 352 1.073 len_pulse[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.594 353 1.073 len_pulse[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.594 354 1.073 len_pulse[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.594 355 1.076 counter_shift[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.591 356 1.076 counter_shift[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.591 357 1.076 counter_shift[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.591 358 1.076 counter_shift[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.591 359 1.076 counter_shift[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.591 360 1.101 counter_shift[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.566 361 1.101 counter_shift[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.566 362 1.101 counter_shift[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.566 363 1.101 counter_shift[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.566 364 1.101 counter_shift[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.566 365 1.149 len_pulse[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.518 366 1.149 len_pulse[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.518 367 1.149 len_pulse[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.518 368 1.149 len_pulse[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.518 369 1.149 len_pulse[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.518 370 1.149 len_pulse[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.518 371 1.150 len_pulse[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.517 372 1.150 len_pulse[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.517 373 1.150 len_pulse[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.517 374 1.150 len_pulse[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.517 375 1.150 len_pulse[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.517 376 1.178 len_pulse[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.489 377 1.178 len_pulse[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.489 378 1.178 len_pulse[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.489 379 1.178 len_pulse[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.489 380 1.178 len_pulse[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.489 381 1.194 counter_shift[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.473 382 1.194 counter_shift[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.473 383 1.194 counter_shift[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.473 384 1.194 counter_shift[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.473 385 1.194 counter_shift[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.473 386 1.194 counter_shift[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.473 387 1.195 len_pulse[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.472 388 1.195 len_pulse[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.472 389 1.195 len_pulse[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.472 390 1.195 len_pulse[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.472 391 1.195 len_pulse[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.472 392 1.195 len_pulse[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.472 393 1.210 counter_shift[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.457 394 1.210 counter_shift[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.457 395 1.210 counter_shift[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.457 396 1.210 counter_shift[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.457 397 1.210 counter_shift[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.457 398 1.210 counter_shift[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.457 399 1.220 counter_shift[4] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.447 400 1.220 counter_shift[4] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.447 401 1.220 counter_shift[4] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.447 402 1.220 counter_shift[4] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.447 403 1.220 counter_shift[4] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.447 404 1.220 counter_shift[4] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.447 405 1.238 counter_shift[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.429 406 1.238 counter_shift[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.429 407 1.238 counter_shift[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.429 408 1.238 counter_shift[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.429 409 1.238 counter_shift[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.429 410 1.245 len_pulse[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.422 411 1.245 len_pulse[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.422 412 1.245 len_pulse[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.422 413 1.245 len_pulse[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.422 414 1.245 len_pulse[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.422 415 1.245 len_pulse[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.422 416 1.245 len_pulse[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.422 417 1.245 len_pulse[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.422 418 1.245 len_pulse[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.422 419 1.245 len_pulse[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.422 420 1.245 len_pulse[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.422 421 1.245 len_pulse[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.422 422 1.248 len_pulse[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.419 423 1.248 len_pulse[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.419 424 1.248 len_pulse[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.419 425 1.248 len_pulse[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.419 426 1.248 len_pulse[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.419 427 1.248 len_pulse[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.419 428 1.251 counter_shift[9] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.416 429 1.251 counter_shift[9] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.416 430 1.251 counter_shift[9] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.416 431 1.251 counter_shift[9] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.416 432 1.251 counter_shift[9] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.416 433 1.271 len_pulse[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.396 434 1.271 len_pulse[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.396 435 1.271 len_pulse[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.396 436 1.271 len_pulse[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.396 437 1.271 len_pulse[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.396 438 1.271 len_pulse[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.396 439 1.294 counter_shift[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.373 440 1.294 counter_shift[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.373 441 1.294 counter_shift[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.373 442 1.294 counter_shift[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.373 443 1.294 counter_shift[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.373 444 1.343 counter_shift[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.324 445 1.343 counter_shift[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.324 446 1.343 counter_shift[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.324 447 1.343 counter_shift[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.324 448 1.343 counter_shift[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.324 449 1.343 counter_shift[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.324 450 1.357 counter_shift[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.310 451 1.357 counter_shift[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.310 452 1.357 counter_shift[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.310 453 1.357 counter_shift[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.310 454 1.357 counter_shift[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.310 455 1.357 counter_shift[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.310 456 1.363 counter_shift[10] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.304 457 1.363 counter_shift[10] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.304 458 1.363 counter_shift[10] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.304 459 1.363 counter_shift[10] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.304 460 1.363 counter_shift[10] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.304 461 1.363 counter_shift[10] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.304 462 1.367 len_pulse[11] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.300 463 1.367 len_pulse[11] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.300 464 1.367 len_pulse[11] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.300 465 1.367 len_pulse[11] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.300 466 1.367 len_pulse[11] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.300 467 1.371 len_pulse[9] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.296 468 1.371 len_pulse[9] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.296 469 1.371 len_pulse[9] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.296 470 1.371 len_pulse[9] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.296 471 1.371 len_pulse[9] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.296 472 1.371 len_pulse[9] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.296 473 1.386 len_pulse[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.281 474 1.386 len_pulse[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.281 475 1.386 len_pulse[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.281 476 1.386 len_pulse[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.281 477 1.386 len_pulse[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.281 478 1.395 len_pulse[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.272 479 1.395 len_pulse[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.272 480 1.395 len_pulse[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.272 481 1.395 len_pulse[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.272 482 1.395 len_pulse[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.272 483 1.395 len_pulse[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.272 484 1.402 len_pulse[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.265 485 1.402 len_pulse[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.265 486 1.402 len_pulse[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.265 487 1.402 len_pulse[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.265 488 1.402 len_pulse[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.265 489 1.402 len_pulse[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.265 490 1.445 len_pulse[9] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.222 491 1.445 len_pulse[9] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.222 492 1.445 len_pulse[9] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.222 493 1.445 len_pulse[9] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.222 494 1.445 len_pulse[9] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.222 495 1.450 len_pulse[10] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.217 496 1.450 len_pulse[10] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.217 497 1.450 len_pulse[10] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.217 498 1.450 len_pulse[10] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.217 499 1.450 len_pulse[10] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.217 500 1.450 len_pulse[10] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.217 501 1.459 counter_shift[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.208 502 1.459 counter_shift[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.208 503 1.459 counter_shift[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.208 504 1.459 counter_shift[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.208 505 1.459 counter_shift[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.208 506 1.459 counter_shift[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.208 507 1.483 counter_shift[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.184 508 1.483 counter_shift[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.184 509 1.483 counter_shift[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.184 510 1.483 counter_shift[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.184 511 1.483 counter_shift[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.184 512 1.484 counter_shift[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.183 513 1.484 counter_shift[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.183 514 1.484 counter_shift[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.183 515 1.484 counter_shift[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.183 516 1.484 counter_shift[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.183 517 1.484 counter_shift[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.183 518 1.533 len_pulse[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.134 519 1.533 len_pulse[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.134 520 1.533 len_pulse[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.134 521 1.533 len_pulse[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.134 522 1.533 len_pulse[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.134 523 1.533 len_pulse[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.134 524 1.537 counter_shift[0] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 8.130 525 1.539 counter_shift[0] zcd_input_out CLK_IN CLK_IN 10.000 0.000 8.128 526 1.542 counter_shift[0] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 8.125 527 1.545 len_pulse[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.122 528 1.545 len_pulse[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.122 529 1.545 len_pulse[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.122 530 1.545 len_pulse[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.122 531 1.545 len_pulse[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.122 532 1.561 len_pulse[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.106 533 1.561 len_pulse[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.106 534 1.561 len_pulse[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.106 535 1.561 len_pulse[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.106 536 1.561 len_pulse[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.106 537 1.561 len_pulse[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.106 538 1.621 counter_shift[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.046 539 1.621 counter_shift[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.046 540 1.621 counter_shift[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.046 541 1.621 counter_shift[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.046 542 1.621 counter_shift[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.046 543 1.621 counter_shift[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.046 544 1.634 counter_shift[9] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 8.033 545 1.634 counter_shift[9] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 8.033 546 1.634 counter_shift[9] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 8.033 547 1.634 counter_shift[9] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 8.033 548 1.634 counter_shift[9] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 8.033 549 1.634 counter_shift[9] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 8.033 550 1.641 len_pulse[0] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.026 551 1.641 len_pulse[0] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.026 552 1.641 len_pulse[0] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.026 553 1.641 len_pulse[0] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.026 554 1.641 len_pulse[0] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.026 555 1.649 counter_shift[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 8.018 556 1.649 counter_shift[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 8.018 557 1.649 counter_shift[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 8.018 558 1.649 counter_shift[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 8.018 559 1.649 counter_shift[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 8.018 560 1.681 counter_shift[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.986 561 1.681 counter_shift[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.986 562 1.681 counter_shift[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.986 563 1.681 counter_shift[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.986 564 1.681 counter_shift[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.986 565 1.681 counter_shift[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.986 566 1.688 len_pulse[9] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.979 567 1.690 len_pulse[9] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.977 568 1.693 len_pulse[9] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.974 569 1.750 len_pulse[11] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.917 570 1.750 len_pulse[11] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.917 571 1.750 len_pulse[11] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.917 572 1.750 len_pulse[11] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.917 573 1.750 len_pulse[11] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.917 574 1.750 len_pulse[11] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.917 575 1.759 counter_shift[10] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.908 576 1.759 counter_shift[10] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.908 577 1.759 counter_shift[10] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.908 578 1.759 counter_shift[10] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.908 579 1.759 counter_shift[10] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.908 580 1.769 len_pulse[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.898 581 1.769 len_pulse[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.898 582 1.769 len_pulse[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.898 583 1.769 len_pulse[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.898 584 1.769 len_pulse[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.898 585 1.769 len_pulse[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.898 586 1.788 len_pulse[2] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.879 587 1.790 len_pulse[2] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.877 588 1.791 len_pulse[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.876 589 1.791 len_pulse[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.876 590 1.791 len_pulse[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.876 591 1.791 len_pulse[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.876 592 1.791 len_pulse[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.876 593 1.793 len_pulse[2] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.874 594 1.798 len_pulse[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.869 595 1.798 len_pulse[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.869 596 1.798 len_pulse[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.869 597 1.798 len_pulse[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.869 598 1.798 len_pulse[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.869 599 1.832 len_pulse[9] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.835 600 1.832 len_pulse[9] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.835 601 1.832 len_pulse[9] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.835 602 1.832 len_pulse[9] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.835 603 1.832 len_pulse[9] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.835 604 1.832 len_pulse[9] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.835 605 1.846 len_pulse[10] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.821 606 1.846 len_pulse[10] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.821 607 1.846 len_pulse[10] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.821 608 1.846 len_pulse[10] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.821 609 1.846 len_pulse[10] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.821 610 1.866 counter_shift[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.801 611 1.866 counter_shift[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.801 612 1.866 counter_shift[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.801 613 1.866 counter_shift[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.801 614 1.866 counter_shift[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.801 615 1.866 counter_shift[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.801 616 1.884 len_pulse[0] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.783 617 1.886 len_pulse[0] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.781 618 1.889 len_pulse[0] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.778 619 1.920 counter_shift[9] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.747 620 1.920 counter_shift[9] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.747 621 1.920 counter_shift[9] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.747 622 1.920 counter_shift[9] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.747 623 1.920 counter_shift[9] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.747 624 1.929 len_pulse[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.738 625 1.929 len_pulse[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.738 626 1.929 len_pulse[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.738 627 1.929 len_pulse[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.738 628 1.929 len_pulse[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.738 629 1.932 len_pulse[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.735 630 1.932 len_pulse[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.735 631 1.932 len_pulse[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.735 632 1.932 len_pulse[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.735 633 1.932 len_pulse[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.735 634 1.932 len_pulse[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.735 635 1.934 len_pulse[4] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.733 636 1.934 len_pulse[4] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.733 637 1.934 len_pulse[4] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.733 638 1.934 len_pulse[4] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.733 639 1.934 len_pulse[4] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.733 640 1.957 len_pulse[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.710 641 1.957 len_pulse[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.710 642 1.957 len_pulse[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.710 643 1.957 len_pulse[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.710 644 1.957 len_pulse[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.710 645 1.977 counter_shift[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.690 646 1.977 counter_shift[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.690 647 1.977 counter_shift[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.690 648 1.977 counter_shift[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.690 649 1.977 counter_shift[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.690 650 2.002 counter_shift[10] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.665 651 2.004 counter_shift[10] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.663 652 2.007 counter_shift[10] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.660 653 2.017 counter_shift[8] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.650 654 2.017 counter_shift[8] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.650 655 2.017 counter_shift[8] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.650 656 2.017 counter_shift[8] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.650 657 2.017 counter_shift[8] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.650 658 2.028 len_pulse[0] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.639 659 2.028 len_pulse[0] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.639 660 2.028 len_pulse[0] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.639 661 2.028 len_pulse[0] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.639 662 2.028 len_pulse[0] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.639 663 2.028 len_pulse[0] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.639 664 2.032 counter_shift[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.635 665 2.032 counter_shift[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.635 666 2.032 counter_shift[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.635 667 2.032 counter_shift[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.635 668 2.032 counter_shift[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.635 669 2.032 counter_shift[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.635 670 2.034 len_pulse[7] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.633 671 2.036 len_pulse[7] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.631 672 2.039 len_pulse[7] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.628 673 2.041 len_pulse[8] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.626 674 2.043 len_pulse[8] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.624 675 2.046 len_pulse[8] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.621 676 2.089 len_pulse[10] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.578 677 2.091 len_pulse[10] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.576 678 2.094 len_pulse[10] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.573 679 2.146 len_pulse[11] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.521 680 2.146 len_pulse[11] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.521 681 2.146 len_pulse[11] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.521 682 2.146 len_pulse[11] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.521 683 2.146 len_pulse[11] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.521 684 2.146 counter_shift[10] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.521 685 2.146 counter_shift[10] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.521 686 2.146 counter_shift[10] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.521 687 2.146 counter_shift[10] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.521 688 2.146 counter_shift[10] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.521 689 2.146 counter_shift[10] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.521 690 2.165 len_pulse[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.502 691 2.165 len_pulse[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.502 692 2.165 len_pulse[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.502 693 2.165 len_pulse[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.502 694 2.165 len_pulse[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.502 695 2.172 len_pulse[3] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.495 696 2.174 len_pulse[3] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.493 697 2.177 len_pulse[3] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.490 698 2.178 len_pulse[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.489 699 2.178 len_pulse[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.489 700 2.178 len_pulse[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.489 701 2.178 len_pulse[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.489 702 2.178 len_pulse[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.489 703 2.178 len_pulse[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.489 704 2.185 len_pulse[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.482 705 2.185 len_pulse[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.482 706 2.185 len_pulse[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.482 707 2.185 len_pulse[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.482 708 2.185 len_pulse[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.482 709 2.185 len_pulse[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.482 710 2.200 len_pulse[6] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.467 711 2.202 len_pulse[6] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.465 712 2.205 len_pulse[6] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.462 713 2.233 len_pulse[10] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.434 714 2.233 len_pulse[10] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.434 715 2.233 len_pulse[10] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.434 716 2.233 len_pulse[10] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.434 717 2.233 len_pulse[10] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.434 718 2.233 len_pulse[10] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.434 719 2.260 counter_shift[8] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.407 720 2.262 counter_shift[3] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.405 721 2.262 counter_shift[3] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.405 722 2.262 counter_shift[3] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.405 723 2.262 counter_shift[3] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.405 724 2.262 counter_shift[3] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.405 725 2.262 counter_shift[8] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.405 726 2.265 counter_shift[8] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.402 727 2.291 len_pulse[10] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.376 728 2.291 len_pulse[10] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.376 729 2.291 len_pulse[10] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.376 730 2.291 len_pulse[10] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.376 731 2.291 len_pulse[10] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.376 732 2.303 counter_shift[9] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.364 733 2.303 counter_shift[9] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.364 734 2.303 counter_shift[9] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.364 735 2.303 counter_shift[9] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.364 736 2.303 counter_shift[9] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.364 737 2.303 counter_shift[9] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.364 738 2.316 len_pulse[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.351 739 2.316 len_pulse[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.351 740 2.316 len_pulse[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.351 741 2.316 len_pulse[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.351 742 2.316 len_pulse[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.351 743 2.316 len_pulse[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.351 744 2.317 len_pulse[4] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.350 745 2.317 len_pulse[4] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.350 746 2.317 len_pulse[4] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.350 747 2.317 len_pulse[4] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.350 748 2.317 len_pulse[4] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.350 749 2.317 len_pulse[4] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.350 750 2.344 len_pulse[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.323 751 2.344 len_pulse[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.323 752 2.344 len_pulse[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.323 753 2.344 len_pulse[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.323 754 2.344 len_pulse[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.323 755 2.344 len_pulse[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.323 756 2.356 counter_shift[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.311 757 2.356 counter_shift[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.311 758 2.356 counter_shift[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.311 759 2.356 counter_shift[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.311 760 2.356 counter_shift[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.311 761 2.360 counter_shift[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.307 762 2.360 counter_shift[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.307 763 2.360 counter_shift[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.307 764 2.360 counter_shift[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.307 765 2.360 counter_shift[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.307 766 2.360 counter_shift[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.307 767 2.389 len_pulse[11] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.278 768 2.391 len_pulse[11] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.276 769 2.394 len_pulse[11] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.273 770 2.404 counter_shift[8] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.263 771 2.404 counter_shift[8] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.263 772 2.404 counter_shift[8] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.263 773 2.404 counter_shift[8] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.263 774 2.404 counter_shift[8] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.263 775 2.404 counter_shift[8] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.263 776 2.408 len_pulse[1] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.259 777 2.410 len_pulse[1] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.257 778 2.413 len_pulse[1] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.254 779 2.428 counter_shift[2] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.239 780 2.428 counter_shift[2] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.239 781 2.428 counter_shift[2] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.239 782 2.428 counter_shift[2] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.239 783 2.428 counter_shift[2] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.239 784 2.468 len_pulse[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 7.199 785 2.468 len_pulse[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 7.199 786 2.468 len_pulse[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 7.199 787 2.468 len_pulse[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 7.199 788 2.468 len_pulse[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 7.199 789 2.505 counter_shift[3] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 7.162 790 2.507 counter_shift[3] zcd_input_out CLK_IN CLK_IN 10.000 0.000 7.160 791 2.510 counter_shift[3] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 7.157 792 2.533 len_pulse[11] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.134 793 2.533 len_pulse[11] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.134 794 2.533 len_pulse[11] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.134 795 2.533 len_pulse[11] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.134 796 2.533 len_pulse[11] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.134 797 2.533 len_pulse[11] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.134 798 2.552 len_pulse[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.115 799 2.552 len_pulse[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.115 800 2.552 len_pulse[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.115 801 2.552 len_pulse[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.115 802 2.552 len_pulse[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.115 803 2.552 len_pulse[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.115 804 2.649 counter_shift[3] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 7.018 805 2.649 counter_shift[3] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 7.018 806 2.649 counter_shift[3] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 7.018 807 2.649 counter_shift[3] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 7.018 808 2.649 counter_shift[3] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 7.018 809 2.649 counter_shift[3] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 7.018 810 2.671 counter_shift[2] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 6.996 811 2.673 counter_shift[2] zcd_input_out CLK_IN CLK_IN 10.000 0.000 6.994 812 2.674 len_pulse[10] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.993 813 2.674 len_pulse[10] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.993 814 2.674 len_pulse[10] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.993 815 2.674 len_pulse[10] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.993 816 2.674 len_pulse[10] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.993 817 2.674 len_pulse[10] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.993 818 2.676 counter_shift[2] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 6.991 819 2.699 counter_shift[9] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.968 820 2.699 counter_shift[9] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.968 821 2.699 counter_shift[9] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.968 822 2.699 counter_shift[9] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.968 823 2.699 counter_shift[9] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.968 824 2.713 len_pulse[4] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.954 825 2.713 len_pulse[4] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.954 826 2.713 len_pulse[4] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.954 827 2.713 len_pulse[4] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.954 828 2.713 len_pulse[4] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.954 829 2.739 counter_shift[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.928 830 2.739 counter_shift[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.928 831 2.739 counter_shift[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.928 832 2.739 counter_shift[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.928 833 2.739 counter_shift[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.928 834 2.739 counter_shift[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.928 835 2.756 counter_shift[1] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.911 836 2.756 counter_shift[1] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.911 837 2.756 counter_shift[1] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.911 838 2.756 counter_shift[1] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.911 839 2.756 counter_shift[1] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.911 840 2.815 counter_shift[2] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.852 841 2.815 counter_shift[2] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.852 842 2.815 counter_shift[2] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.852 843 2.815 counter_shift[2] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.852 844 2.815 counter_shift[2] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.852 845 2.815 counter_shift[2] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.852 846 2.828 counter_shift[10] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.839 847 2.828 counter_shift[10] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.839 848 2.828 counter_shift[10] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.839 849 2.828 counter_shift[10] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.839 850 2.828 counter_shift[10] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.839 851 2.851 len_pulse[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.816 852 2.851 len_pulse[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.816 853 2.851 len_pulse[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.816 854 2.851 len_pulse[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.816 855 2.851 len_pulse[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.816 856 2.851 len_pulse[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.816 857 2.893 counter_shift[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.774 858 2.893 counter_shift[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.774 859 2.893 counter_shift[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.774 860 2.893 counter_shift[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.774 861 2.893 counter_shift[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.774 862 2.942 counter_shift[9] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 6.725 863 2.944 counter_shift[9] zcd_input_out CLK_IN CLK_IN 10.000 0.000 6.723 864 2.947 counter_shift[9] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 6.720 865 2.956 len_pulse[4] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 6.711 866 2.958 len_pulse[4] zcd_input_out CLK_IN CLK_IN 10.000 0.000 6.709 867 2.961 len_pulse[4] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 6.706 868 2.999 counter_shift[1] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 6.668 869 3.001 counter_shift[1] zcd_input_out CLK_IN CLK_IN 10.000 0.000 6.666 870 3.004 counter_shift[1] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 6.663 871 3.086 counter_shift[9] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.581 872 3.086 counter_shift[9] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.581 873 3.086 counter_shift[9] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.581 874 3.086 counter_shift[9] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.581 875 3.086 counter_shift[9] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.581 876 3.086 counter_shift[9] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.581 877 3.100 len_pulse[4] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.567 878 3.100 len_pulse[4] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.567 879 3.100 len_pulse[4] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.567 880 3.100 len_pulse[4] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.567 881 3.100 len_pulse[4] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.567 882 3.100 len_pulse[4] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.567 883 3.135 counter_shift[7] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.532 884 3.135 counter_shift[7] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.532 885 3.135 counter_shift[7] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.532 886 3.135 counter_shift[7] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.532 887 3.135 counter_shift[7] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.532 888 3.143 counter_shift[1] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.524 889 3.143 counter_shift[1] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.524 890 3.143 counter_shift[1] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.524 891 3.143 counter_shift[1] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.524 892 3.143 counter_shift[1] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.524 893 3.143 counter_shift[1] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.524 894 3.211 counter_shift[10] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.456 895 3.211 counter_shift[10] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.456 896 3.211 counter_shift[10] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.456 897 3.211 counter_shift[10] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.456 898 3.211 counter_shift[10] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.456 899 3.211 counter_shift[10] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.456 900 3.247 len_pulse[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.420 901 3.247 len_pulse[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.420 902 3.247 len_pulse[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.420 903 3.247 len_pulse[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.420 904 3.247 len_pulse[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.420 905 3.276 counter_shift[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.391 906 3.276 counter_shift[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.391 907 3.276 counter_shift[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.391 908 3.276 counter_shift[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.391 909 3.276 counter_shift[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.391 910 3.276 counter_shift[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.391 911 3.310 counter_shift[4] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.357 912 3.310 counter_shift[4] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.357 913 3.310 counter_shift[4] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.357 914 3.310 counter_shift[4] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.357 915 3.310 counter_shift[4] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.357 916 3.378 counter_shift[7] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 6.289 917 3.380 counter_shift[7] zcd_input_out CLK_IN CLK_IN 10.000 0.000 6.287 918 3.383 counter_shift[7] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 6.284 919 3.459 counter_shift[5] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 6.208 920 3.459 counter_shift[5] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 6.208 921 3.459 counter_shift[5] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 6.208 922 3.459 counter_shift[5] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 6.208 923 3.459 counter_shift[5] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 6.208 924 3.490 len_pulse[5] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 6.177 925 3.492 len_pulse[5] zcd_input_out CLK_IN CLK_IN 10.000 0.000 6.175 926 3.495 len_pulse[5] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 6.172 927 3.514 r_count[4] len_pulse[7] CLK_IN CLK_IN 10.000 0.000 6.153 928 3.514 r_count[4] len_pulse[6] CLK_IN CLK_IN 10.000 0.000 6.153 929 3.514 r_count[4] len_pulse[9] CLK_IN CLK_IN 10.000 0.000 6.153 930 3.514 r_count[4] len_pulse[8] CLK_IN CLK_IN 10.000 0.000 6.153 931 3.514 r_count[4] len_pulse[10] CLK_IN CLK_IN 10.000 0.000 6.153 932 3.522 counter_shift[7] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.145 933 3.522 counter_shift[7] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.145 934 3.522 counter_shift[7] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.145 935 3.522 counter_shift[7] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.145 936 3.522 counter_shift[7] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.145 937 3.522 counter_shift[7] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.145 938 3.527 r_count[4] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 6.140 939 3.531 r_count[4] len_pulse[7] CLK_IN CLK_IN 10.000 0.000 6.136 940 3.531 r_count[4] len_pulse[6] CLK_IN CLK_IN 10.000 0.000 6.136 941 3.531 r_count[4] len_pulse[9] CLK_IN CLK_IN 10.000 0.000 6.136 942 3.531 r_count[4] len_pulse[8] CLK_IN CLK_IN 10.000 0.000 6.136 943 3.531 r_count[4] len_pulse[10] CLK_IN CLK_IN 10.000 0.000 6.136 944 3.544 r_count[4] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 6.123 945 3.600 len_pulse[5] switch_delay CLK_IN CLK_IN 10.000 0.000 6.067 946 3.634 len_pulse[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 6.033 947 3.634 len_pulse[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 6.033 948 3.634 len_pulse[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 6.033 949 3.634 len_pulse[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 6.033 950 3.634 len_pulse[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 6.033 951 3.634 len_pulse[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 6.033 952 3.672 counter_shift[6] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 5.995 953 3.672 counter_shift[6] counter_shift[3] CLK_IN CLK_IN 10.000 0.000 5.995 954 3.672 counter_shift[6] counter_shift[1] CLK_IN CLK_IN 10.000 0.000 5.995 955 3.672 counter_shift[6] counter_shift[0] CLK_IN CLK_IN 10.000 0.000 5.995 956 3.672 counter_shift[6] counter_shift[4] CLK_IN CLK_IN 10.000 0.000 5.995 957 3.693 counter_shift[4] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 5.974 958 3.693 counter_shift[4] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 5.974 959 3.693 counter_shift[4] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 5.974 960 3.693 counter_shift[4] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 5.974 961 3.693 counter_shift[4] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 5.974 962 3.693 counter_shift[4] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 5.974 963 3.746 r_count[1] len_pulse[7] CLK_IN CLK_IN 10.000 0.000 5.921 964 3.746 r_count[1] len_pulse[6] CLK_IN CLK_IN 10.000 0.000 5.921 965 3.746 r_count[1] len_pulse[9] CLK_IN CLK_IN 10.000 0.000 5.921 966 3.746 r_count[1] len_pulse[8] CLK_IN CLK_IN 10.000 0.000 5.921 967 3.746 r_count[1] len_pulse[10] CLK_IN CLK_IN 10.000 0.000 5.921 968 3.759 r_count[1] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 5.908 969 3.799 r_count[1] len_pulse[7] CLK_IN CLK_IN 10.000 0.000 5.868 970 3.799 r_count[1] len_pulse[6] CLK_IN CLK_IN 10.000 0.000 5.868 971 3.799 r_count[1] len_pulse[9] CLK_IN CLK_IN 10.000 0.000 5.868 972 3.799 r_count[1] len_pulse[8] CLK_IN CLK_IN 10.000 0.000 5.868 973 3.799 r_count[1] len_pulse[10] CLK_IN CLK_IN 10.000 0.000 5.868 974 3.812 r_count[1] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 5.855 975 3.842 counter_shift[5] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 5.825 976 3.842 counter_shift[5] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 5.825 977 3.842 counter_shift[5] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 5.825 978 3.842 counter_shift[5] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 5.825 979 3.842 counter_shift[5] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 5.825 980 3.842 counter_shift[5] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 5.825 981 3.879 r_count[5] len_pulse[7] CLK_IN CLK_IN 10.000 0.000 5.788 982 3.879 r_count[5] len_pulse[6] CLK_IN CLK_IN 10.000 0.000 5.788 983 3.879 r_count[5] len_pulse[9] CLK_IN CLK_IN 10.000 0.000 5.788 984 3.879 r_count[5] len_pulse[8] CLK_IN CLK_IN 10.000 0.000 5.788 985 3.879 r_count[5] len_pulse[10] CLK_IN CLK_IN 10.000 0.000 5.788 986 3.892 r_count[5] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 5.775 987 3.901 r_count[9] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 5.766 988 3.914 r_count[9] len_pulse[11] CLK_IN CLK_IN 10.000 0.000 5.753 989 3.915 counter_shift[6] current_stage.set_level CLK_IN CLK_IN 10.000 0.000 5.752 990 3.917 counter_shift[6] zcd_input_out CLK_IN CLK_IN 10.000 0.000 5.750 991 3.920 counter_shift[6] current_stage.wait_high_low CLK_IN CLK_IN 10.000 0.000 5.747 992 4.038 len_pulse[8] switch_delay CLK_IN CLK_IN 10.000 0.000 5.629 993 4.059 counter_shift[6] counter_shift[5] CLK_IN CLK_IN 10.000 0.000 5.608 994 4.059 counter_shift[6] counter_shift[6] CLK_IN CLK_IN 10.000 0.000 5.608 995 4.059 counter_shift[6] counter_shift[7] CLK_IN CLK_IN 10.000 0.000 5.608 996 4.059 counter_shift[6] counter_shift[8] CLK_IN CLK_IN 10.000 0.000 5.608 997 4.059 counter_shift[6] counter_shift[9] CLK_IN CLK_IN 10.000 0.000 5.608 998 4.059 counter_shift[6] counter_shift[10] CLK_IN CLK_IN 10.000 0.000 5.608 999 4.089 counter_shift[4] counter_shift[2] CLK_IN CLK_IN 10.000 0.000 5.578 1000 1 Quote Share this post Link to post Share on other sites More sharing options...
fpga_dev 11 December 15, 2025 Posted December 15, 2025 · Report post Ну при всем уважении я бы не назвал GW1N современной. Без логики быстрого переноса вся арифметика просто обречена быть медленной. Я смотрю у вас макс. 5 уровней логики и примерно 50/50 logic/routing delay что в принципе нормально и 100Mhz это ближе к истине чем 50. Что можно попробовать сделать: попробуйте переписать код чтобы избегать сложения/вычитания/сравнения на больше/меньше между двумя сигналами. Напр. for(i = 0; i< n; i++) медленно for(i = 0; i != n; i++) быстрее for(i = n; i != 0; i--) еще лучше Сравнение на больше/меньше между двумя 11-битными сигналами это нетривиальная функция от 22 битов, сравнение с константой это только 11 бит. Сравнение на равно/не равно попроще но все равно для двух переменных это 3 уровня логики, для сравнения с константой это только 2 уровня. Но если совсем припрет, то обычный подход к сложению/вычитанию длинных чисел это поделить их на части и считать их со сдвигом в один цикл (напр. пополам, сначала складывать/вычитать нижнюю половину, записать перенос в регистр затем верхнюю в следующем цикле). Но в вашем случае это может многого не дать, меньше 3 уровней все равно вряд ли получится и потом у вас задержки routing начнут доминировать. Quote Share this post Link to post Share on other sites More sharing options...
gridinp 10 December 15, 2025 Posted December 15, 2025 · Report post может быть попробуйте сделать очень простой проект и посмореть Fmax, боюсь что 150-200 мгц вы не получите от max2, это для неё многовато Quote Share this post Link to post Share on other sites More sharing options...
Nikolas72_91 1 December 15, 2025 Posted December 15, 2025 · Report post 1 час назад, gridinp сказал: может быть попробуйте сделать очень простой проект и посмореть Fmax, боюсь что 150-200 мгц вы не получите от max2, это для неё многовато Попробую скомпилировать на max5 и max10 и посмотреть разницу. Раньше сравнивал с max10, но не сильно большая разница была. Quote Share this post Link to post Share on other sites More sharing options...
Nikolas72_91 1 December 15, 2025 Posted December 15, 2025 · Report post 4 часа назад, fpga_dev сказал: Ну при всем уважении я бы не назвал GW1N современной. Без логики быстрого переноса вся арифметика просто обречена быть медленной. Я смотрю у вас макс. 5 уровней логики и примерно 50/50 logic/routing delay что в принципе нормально и 100Mhz это ближе к истине чем 50. Что можно попробовать сделать: попробуйте переписать код чтобы избегать сложения/вычитания/сравнения на больше/меньше между двумя сигналами. Напр. for(i = 0; i< n; i++) медленно for(i = 0; i != n; i++) быстрее for(i = n; i != 0; i--) еще лучше Сравнение на больше/меньше между двумя 11-битными сигналами это нетривиальная функция от 22 битов, сравнение с константой это только 11 бит. Сравнение на равно/не равно попроще но все равно для двух переменных это 3 уровня логики, для сравнения с константой это только 2 уровня. Но если совсем припрет, то обычный подход к сложению/вычитанию длинных чисел это поделить их на части и считать их со сдвигом в один цикл (напр. пополам, сначала складывать/вычитать нижнюю половину, записать перенос в регистр затем верхнюю в следующем цикле). Но в вашем случае это может многого не дать, меньше 3 уровней все равно вряд ли получится и потом у вас задержки routing начнут доминировать. А что за логика быстрого переноса? Это по типу FIFO? До этого была написана допустимая частота 70 но раз у меня тактовый генератор только 50 и 100 мгц есть, то промежутки не учитывал. Вчера пробовал сделать ticks_phase_shift как константу, но, что то не вышло пока. Буду разбираться. Как сделать, чтобы не было операций сложения и вычитания или сравнений пока не соображу как сделать, почитаю, что нибудь еще для информации. На плис пишу на уровне можно почти сказать, чуть выше новичка. Quote Share this post Link to post Share on other sites More sharing options...
Yuri124 6 December 15, 2025 Posted December 15, 2025 · Report post On 12/15/2025 at 10:41 AM, Nikolas72_91 said: А что за логика быстрого переноса? Это по типу FIFO? смотрите схему ускоренного переноса в сумматорах. Quote Share this post Link to post Share on other sites More sharing options...
gridinp 10 December 15, 2025 Posted December 15, 2025 · Report post 1 час назад, Nikolas72_91 сказал: А что за логика быстрого переноса? Quote Share this post Link to post Share on other sites More sharing options...
fpga_dev 11 December 15, 2025 Posted December 15, 2025 (edited) · Report post 1 hour ago, Nikolas72_91 said: Как сделать, чтобы не было операций сложения и вычитания или сравнений пока не соображу как сделать Ну у вас в коде есть такое: 15 hours ago, Nikolas72_91 said: if counter_shift = len_pulse then -- после выставленной задержки, подаём на выход 0 или 1 ... counter_shift <= 0; elsif counter_shift < len_pulse then counter_shift <= counter_shift + 1; ... end if; Очевидно что counter_shift сбрасывается в 0 когда он доходит до len_pulse соответственно он не сможет стать больше len_pulse, но только если только последний не меняется в меньшую сторону в процессе счета. (Кстати ваш код тоже сломается в этом случае, проверьте! ) Тогда вторая проверка на < не нужна. Можно попробовать что нибудь типа: if counter_shift = len_pulse_reg then ... counter_shift <= 0; len_pulse_reg <= len_pulse; else counter_shift <= counter_shift + 1; ... end if; или считать в обратную сторону: if counter_shift = 0 then counter_shift <= len_pulse; else counter_shift <= counter_shift - 1; end if; только имейте в виду что эти фрагменты слегка функционально отличаются от вашего кода (счетчик сравнивается не с текущим значением а со слегка задержанным) Edited December 15, 2025 by fpga_dev Quote Share this post Link to post Share on other sites More sharing options...
iosifk 3 December 15, 2025 Posted December 15, 2025 · Report post В 14.12.2025 в 13:27, fpga_dev сказал: Детально не вникал но несколько соображений: Самая длинная цепочка у васчто представляет из себя 2 12и битных сумматора один за другим. Если диапазон регулирования 100%, то это так. А на самом деле нужно ли 100%? Скажем при 30% регулирования, 70% будет константой, а значит длина цепочек и счетчиков уже не будет критичной... Quote Share this post Link to post Share on other sites More sharing options...
Nikolas72_91 1 December 17, 2025 Posted December 17, 2025 · Report post В 15.12.2025 в 13:54, fpga_dev сказал: Ну у вас в коде есть такое: Очевидно что counter_shift сбрасывается в 0 когда он доходит до len_pulse соответственно он не сможет стать больше len_pulse, но только если только последний не меняется в меньшую сторону в процессе счета. (Кстати ваш код тоже сломается в этом случае, проверьте! ) Тогда вторая проверка на < не нужна. Можно попробовать что нибудь типа: if counter_shift = len_pulse_reg then ... counter_shift <= 0; len_pulse_reg <= len_pulse; else counter_shift <= counter_shift + 1; ... end if; или считать в обратную сторону: if counter_shift = 0 then counter_shift <= len_pulse; else counter_shift <= counter_shift - 1; end if; только имейте в виду что эти фрагменты слегка функционально отличаются от вашего кода (счетчик сравнивается не с текущим значением а со слегка задержанным) Здравствуйте, всем спасибо за все возможные подсказки, внес некоторые изменения частота выросла до 113 МГц, если сделать счетчик на генераторе фазового сдвига в минус до 0 частота растет до 133 МГц, что очень хорошо, если использовать более быстрые плис, то можно еще частоту поднять. Но проблема работа немного ломается, пока не нашел решения как исправить. Со счетом до 0 вот так получилось. Ну и скрины. С ускоренным переносом пока не разобрался. Еле нашел примеры, пока сложновато выглядит. Пробовал написать сравнение констант без необходимости использования тактовой частоты по примерам которые нашел, но сильно разницы не увидел в скорости. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity Driver is generic ( N : integer :=2047; --Разрядность счетчика FREQ_CLK : integer := 100; -- CLK input 50 MHz phase_shift : integer := 300 -- смещение опережения фазы в нсек ); Port ( zcd_input : in std_logic; -- ZCD Feedback off_signal : in std_logic; -- OFF signal input CLK_IN : in std_logic; -- CLK input 50 MHz DRIVER_OUT : out std_logic -- signal output ); end Driver; architecture Behavioral of Driver is type state_type is (set_level, wait_high_low, wait_low_high); -- описание машины состояний signal current_stage : state_type; signal counter_shift : integer range 0 to N := 0; -- внутренний счетчик signal r_count : integer range 0 to N := 0; signal len_pulse : integer range - N to N := 0; signal TICKS_PHASE_SHIFT : integer range 0 to N := 0; signal shift_reg : std_logic_vector(2 downto 0) := (others=>'0'); signal PERIOD_CLK : integer range 0 to 127 := 0; signal r_count_ena : std_logic; signal all_edge : std_logic; signal zcd_input_out : std_logic; signal switch_disable : std_logic; signal switch_delay : std_logic; begin --Формулы для расчета констант из значений частот --============================================== PERIOD_CLK <= (1000000000/(FREQ_CLK*1000000)); -- расчет периода тактовой частоты TICKS_PHASE_SHIFT <= ((phase_shift/PERIOD_CLK) - 1); --============================================== -- Генератор фазового сдвига --============================================== shift_fsm : process (CLK_IN, zcd_input, TICKS_PHASE_SHIFT, switch_disable, switch_delay) begin if TICKS_PHASE_SHIFT = 0 or switch_disable = '1' or switch_delay = '0' then zcd_input_out <= zcd_input; counter_shift <= 0; current_stage <= set_level; elsif rising_edge(CLK_IN) then case current_stage is when set_level => if counter_shift = 0 then -- после выставленной задержки, подаём на выход 0 или 1 if zcd_input = '1' then zcd_input_out <= '0'; current_stage <= wait_high_low; else zcd_input_out <= '1'; current_stage <= wait_low_high; end if; counter_shift <= len_pulse; else counter_shift <= counter_shift - 1; current_stage <= set_level; end if; when wait_high_low => -- ждем переключения 1 на 0 и возвращаемся в set_level if zcd_input = '1' then current_stage <= wait_high_low; else current_stage <= set_level; end if; when wait_low_high => -- ждем переключения 0 на 1 и возвращаемся в set_level if zcd_input = '0' then current_stage <= wait_low_high; else current_stage <= set_level; end if; when others => current_stage <= set_level; end case; end if; end process shift_fsm; --============================================== -- Детектор фронтов --============================================== edge_detector : process(CLK_IN) begin if(rising_edge(CLK_IN)) then shift_reg <= shift_reg(1 downto 0) & zcd_input; -- _________|-------|________ end if; all_edge <= shift_reg(1) xor shift_reg(0); -- __________п______п________ выдает короткий импульс по возрастающему и спадающему фронту входного сигнала end process edge_detector; --============================================== -- Измеритель длительности полупериодов --============================================== pulse_counter : process(CLK_IN, off_signal) begin if(off_signal='0') then -- обнуление всех сигналов и счетчиков при 0 reset асинхронно r_count_ena <= '0'; r_count <= 0; len_pulse <= 0; elsif(rising_edge(CLK_IN)) then -- по возрастающему фронту clk и детектору возрастающего фронта устанавливаюся сигналы в разрешения работы счетчика и вывод данных в регистр хранения if(all_edge='1') then r_count_ena <= '1'; -- установка сигнала разрешения счета r_count <= 0; -- сброс счетчика по детекору фронтов 0 len_pulse <= r_count - TICKS_PHASE_SHIFT; elsif(r_count_ena='1') then r_count <= r_count + 1; -- если разрешающий сигнал 1 то начинается счет end if; end if; end process pulse_counter; --============================================== --Сравнение 2х полупериодов для сброса сдвига если частота понижается. --============================================== compare2 : process(all_edge, off_signal, switch_delay) begin if(off_signal = '0' and switch_delay = '0' ) then switch_disable <= '0'; elsif(rising_edge(all_edge)) then if (r_count < len_pulse ) then switch_disable <= '1'; else switch_disable <= '0'; end if; end if; end process compare2; --============================================== -- Задержка разрешения фазового сдвига для стабилизации сигнала --============================================== switch_delay_pr : process(CLK_IN, off_signal) begin if (off_signal = '0') then switch_delay <= '0'; elsif (rising_edge(CLK_IN)) then if ((len_pulse > TICKS_PHASE_SHIFT)) then switch_delay <= '1'; else switch_delay <= '0'; end if; end if; end process switch_delay_pr ; --============================================== -- Вывод сигналов с плис на драйвера --============================================== DRIVER_OUT <= zcd_input_out; --============================================== end Behavioral; Quote Share this post Link to post Share on other sites More sharing options...
dxp 174 December 18, 2025 Posted December 18, 2025 · Report post Пользуйтесь блоками code (</> на панели инструментов) и убирайте длинные портянки под спойлеры (иконка глаза на панели), чтобы они не загомождали пост и не мешали воспринимать написанный текст. Quote Share this post Link to post Share on other sites More sharing options...
fpga_dev 11 December 18, 2025 Posted December 18, 2025 · Report post 14 hours ago, Nikolas72_91 said: С ускоренным переносом пока не разобрался. Еле нашел примеры, пока сложновато выглядит Вам самому ничего делать не надо, он либо есть, либо нет. У MAX II он есть, вам схему привели, у xilinx он тоже есть. У gowin насколько я понял нет. То есть какие то выделенные провода для переноса присутствуют но само вычисление переноса сделано на LUT (он тратит 2 LUT на бит) а не на специальной логике как у других. 15 hours ago, Nikolas72_91 said: use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; Одно из двух, либо std_logic_arith+std_logic_unsigned либо numeric_std. Они оба определяют unsigned и операции с ним но немного по разному. Quote Share this post Link to post Share on other sites More sharing options...
dxp 174 December 18, 2025 Posted December 18, 2025 · Report post 4 часа назад, fpga_dev сказал: само вычисление переноса сделано на LUT (он тратит 2 LUT на бит) а не на специальной логике как у других. У "других" тоже так же сделано -- у Альтеры во всех младших семействах, и не 2 LUT, а базовая LUT4 бьётся на две LUT3, итого 1 LUT на бит. Топологически LE (Logic Element) расположены вплотную друг к другу и организованы быстрые цепи переносов с задержками порядка 100 пс и меньше, получается вполне шустро. А Cyclone I так вообще топология Carry-Select -- в LAB (Logic Array Block) содержится 10 LE, 5 из них вычисляют сумму для случая, когда входящий перенос равен 0, а остальные пять -- для случая, когда перенос 1. Т.е. по сути производится спекулятивное вычисление частичных сумм, и когда реальный сигнал переноса доходит до LAB, там просто выбирается подходящая половинка. По скорости это очень быстрое решение и безо всяких специальных схем вычисления переносов. Quote Share this post Link to post Share on other sites More sharing options...
