[sergey23 0]

Hello I , have built an IP block which creates samples for the DAC in vitis HLS.

Could you help me uderstand If the samples will be delivered properly to the DAC?

pdf and TCL file are attached.

Thanks.

 

#include <ap_int.h>
#include <stdint.h>
#include <math.h>   // sinf
 
// Pack 8 x int16 into one 128-bit word
static inline ap_uint<128> pack8(
    int16_t s0,int16_t s1,int16_t s2,int16_t s3,
    int16_t s4,int16_t s5,int16_t s6,int16_t s7)
{
    ap_uint<128> w = 0;
    w.range( 15,  0) = (ap_uint<16>)s0;
    w.range( 31, 16) = (ap_uint<16>)s1;
    w.range( 47, 32) = (ap_uint<16>)s2;
    w.range( 63, 48) = (ap_uint<16>)s3;
    w.range( 79, 64) = (ap_uint<16>)s4;
    w.range( 95, 80) = (ap_uint<16>)s5;
    w.range(111, 96) = (ap_uint<16>)s6;
    w.range(127,112) = (ap_uint<16>)s7;
    return w;
}
 
void fill_ddr(                           // Top function
    volatile ap_uint<128>* out,          // M_AXI 128-bit (DDR destination)
    uint32_t               n_words,      // << logic pin (set in BD)
    uint16_t               amplitude)    // << logic pin (set in BD)
{
    // Data mover to DDR stays AXI master:
#pragma HLS INTERFACE m_axi     port=out       offset=slave bundle=gmem depth=1024 num_read_outstanding=4 num_write_outstanding=16 max_write_burst_length=64
 
    // Keep an AXI-Lite for ap_ctrl_hs (start/done/idle) and for passing 'out' base address:
#pragma HLS INTERFACE s_axilite port=out       bundle=ctrl
#pragma HLS INTERFACE s_axilite port=return    bundle=ctrl
 
    // Make these plain ports (no register), so they appear as pins in the BD:
#pragma HLS INTERFACE ap_none   port=n_words
#pragma HLS INTERFACE ap_none   port=amplitude
 
    // Tell HLS they won't change during a run (better QoR):
#pragma HLS STABLE   variable=n_words
#pragma HLS STABLE   variable=amplitude
 
    // Clamp amplitude to int16 range
    int16_t A = (amplitude > 0x7FFF) ? 0x7FFF : (int16_t)amplitude;
 
    // Build one 32-sample period: s[n] = A * sin(2*pi*(15/32)*n)
    const float TWO_PI = 6.2831853071795864769f;
    const float STEP   = TWO_PI * (15.0f / 32.0f);
 
    int16_t wav32[32];
#pragma HLS ARRAY_PARTITION variable=wav32 complete dim=1
    for (int n = 0; n < 32; ++n) {
        float xf = (float)A * sinf(STEP * (float)n);
        int tmp = (xf >= 0.0f) ? (int)(xf + 0.5f) : (int)(xf - 0.5f);
        if (tmp >  32767) tmp =  32767;
        if (tmp < -32768) tmp = -32768;
        wav32[n] = (int16_t)tmp;
    }
 
    // Stream out, 8 samples per 128-bit beat, repeating every 32 samples
    uint8_t idx = 0; // 0..31
write_loop:
    for (uint32_t i = 0; i < n_words; i++) {
    #pragma HLS PIPELINE II=1
        ap_uint<128> w = pack8(
            wav32[(idx+0) & 31], wav32[(idx+1) & 31],
            wav32[(idx+2) & 31], wav32[(idx+3) & 31],
            wav32[(idx+4) & 31], wav32[(idx+5) & 31],
            wav32[(idx+6) & 31], wav32[(idx+7) & 31]
        );
        out[i] = w;
        idx = (idx + 8) & 31; // advance 8 samples per beat; wrap at 32
    }
}

 

design_rf_26_fina (1).tcl design_rf_26_final (1).pdf