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файловый ввод/вывод

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lab6 is
	generic(DATA_WIDTH : natural := 9);
	port 
	(
		side             : in  std_logic;
		step             : in  std_logic_vector(DATA_WIDTH-1 downto 0);
		vector           : in  std_logic_vector(DATA_WIDTH-1 downto 0);
		res_p, res_f	  : out std_logic_vector(DATA_WIDTH-1 downto 0)
	);

end entity;

architecture rtl of lab6 is
	procedure inc_d_p(
		vector        : in std_logic_vector;
		side          : in std_logic;
		step          : in std_logic_vector;
	   signal result : out std_logic_vector
	) is
	
	begin
		if (side = '0') then
			result <= std_logic_vector(signed(vector) - signed(step));
		else
			result <= std_logic_vector(signed(vector) + signed(step));
		end if;
	
	end procedure inc_d_p;
	
	function inc_d_f(
		vector : in std_logic_vector;
		side   : in std_logic;
		step   : in std_logic_vector
	) return std_logic_vector is
		variable result : std_logic_vector(vector' range);
	begin
		if (side = '0') then
			result := std_logic_vector(signed(vector) - signed(step));
		else
			result := std_logic_vector(signed(vector) + signed(step));
		end if;
		return result;
    end function inc_d_f;
	 
begin
	inc_d_p(vector, side, step, res_p);
	res_f <= inc_d_f(vector, side, step);
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity lab6_tb is
end entity;

architecture rtl of lab6_tb is
	component lab6 is
		generic(DATA_WIDTH : natural := 9);
			port 
			(
				side             : in  std_logic;
				step             : in  std_logic_vector(DATA_WIDTH-1 downto 0);
				vector           : in  std_logic_vector(DATA_WIDTH-1 downto 0);
				res_p, res_f	  : out std_logic_vector(DATA_WIDTH-1 downto 0)
			);

	end component;
	signal vector, step : std_logic_vector(9-1 downto 0);
	signal side   : std_logic;
	signal p, f : std_logic_vector(9-1 downto 0);
begin
	inst1: component lab6
		generic map(
			DATA_WIDTH => 9
		)
		port map(
			side => side,
			step => step,
			vector => vector,
			res_p => p,
			res_f => f
		);
		
	process is
	begin
		vector <= "110110001";
		side <= '1';
		step <= "000110101";
		wait for 100 ps;
		
		vector <= "110111101";
		side <= '1';
		step <= "000110000";
		wait for 100 ps;
		
		vector <= "101001001";
		side <= '0';
		step <= "000000110";
		wait for 100 ps;
		
		vector <= "000001100";
		side <= '1';
		step <= "000001111";
		wait for 100 ps;
		
		vector <= "001010101";
		side <= '0';
		step <= "000100001";
		wait for 100 ps;
		
		vector <= "001110111";
		side <= '1';
		step <= "000000011";
		wait for 100 ps;
	
	end process;
		
end rtl;

Первый раз работаю с файлами и не знаю как правильно это реализовать. Нужно при помощи Текстового редактора (Text Editor) инструментальной среды разработки ModelSim-Altera реализовать файловый ввод/вывод. Работа с файлами должна осуществляться в тестирующем модуле (TestBench)

Edited by hdus
ошибка в слове

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Пример процесса в тестбенче, считывающего из файла data.txt по два 4-хбитных значения, разделенных пробелом

с периодом SCLKP_period/7

В файле данные выглядят так:

1010 0101

1100 0011

и т.д.

Считанные данные в виде сигналов S_SDP и S_SDN подаются на входы синтезируемого модуля

file file_input : text;

 


--------------------------------------------------------------------------
-- LVDS Input simulation process
--------------------------------------------------------------------------
    LVDS_process :process
     variable v_ILINE     : line;
     variable data_p          : std_logic_vector(3 downto 0);
     variable data_n      : std_logic_vector(3 downto 0);
     variable v_SPACE     : character;
    begin
        wait for 10 us;
        wait until RISING_EDGE(S_SCLKP);
        wait for SCLKP_period/7;
       loop     
         file_open(file_input, "data.txt",  read_mode);
             while not endfile(file_input) loop
                readline(file_input, v_ILINE);
                read(v_ILINE, data_p);
                read(v_ILINE, v_SPACE);           -- read in the space character
                read(v_ILINE, data_n);
                wait for SCLKP_period/7;
                S_SDP <= data_p;
                S_SDN <= data_n;
             end loop;
            file_close(file_input);
       end loop;
    end process;
--------------------------------------------------------------------------

 

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