[IMNO 0]

Здравствуйте!

1. Исправьте пожалуйста, чтобы оно скомпилировалось.

2. Почему нельзя объявить сигналы в теле процедуры?

signal C_S: std_logic;
signal C_R: std_logic;

 

 

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:	20:36:52 04/05/2015 
-- Design Name: 
-- Module Name:	laba_4 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity laba_4 is
port( J: in std_logic;
		K: in std_logic;
		C: in std_logic;
		Q: out std_logic;
		not_Q: out std_logic
	  );

end laba_4;

architecture Behavioral of laba_4 is

-----------------------RS триггер-------------------------------

procedure RSTrigger(		signal S: in std_logic;
								signal R: in std_logic;
								signal Q: out std_logic;
								signal not_Q: out std_logic
							) is
begin

	Q <= not( R or not_Q );
	not_Q <= not( S or Q );

end RSTrigger;

-----------------------RS триггер-------------------------------

-----------------------синхронный RS триггер-------------------------------

procedure CRSTrigger(   signal S: in std_logic;
								signal R: in std_logic;
								signal C: in std_logic;
								signal Q: out std_logic;
								signal not_Q: out std_logic
							) is 
begin

	signal C_S: std_logic;
	signal C_R: std_logic;

	C_S <= S and C;
	C_R <= R and C;

	RSTrigger( C_S, C_R, Q, not_Q );

end CRSTrigger;
-----------------------синхронный RS триггер-------------------------------

-----------------------двухступенчатый RS триггер-------------------------------

procedure TwoRSTrigger( signal S: in std_logic;
								signal R: in std_logic;
								signal C: in std_logic;
								signal Q: out std_logic;
								signal not_Q: out std_logic
							  ) is
begin

	signal not_Q_S: std_logic;
	signal Q_R: std_logic;

	if( C = '1' ) then
		CRSTrigger( S, R, C, Q, not_Q );
		not_Q_S <= not_Q;
		Q_R <= Q;
	else
		CRSTrigger( not_Q_S, Q_R, C, Q, not_Q );
	end if;

end TwoRSTrigger;

-----------------------двухступенчатый RS триггер-------------------------------

-----------------------JK триггер-------------------------------

procedure JKTrigger( signal J: in std_logic;
							signal K: in std_logic;
							signal C: in std_logic;
							signal Q: out std_logic;
							signal not_Q: out std_logic
						  ) is
begin

	signal not_Q_J: std_logic;
	signal Q_K: std_logic;

	not_Q_J <= J and not_Q;
	Q_K <= K and Q;

	TwoRSTrigger( not_Q_J, Q_K, C, Q, not_Q );

end JKTrigger;

-----------------------JK триггер-------------------------------

begin


JKTrigger( J, K, C, Q, not_Q );

end Behavioral;

[Maverick_ 17]

Здравствуйте!

 

Описание портов:

CLK − вход тактовой частоты;

Reset – вход асинхронного сброса;

J – J-вход;

K – K-вход;

Q – выход.

 

library IEEE;
use IEEE.std_logic_1164.all;
entity JK_tr is

      port (J: in STD_LOGIC;
            K:in STD_LOGIC;
            CLK:in STD_LOGIC;
            Reset: in STD_LOGIC;
            Q: out STD_LOGIC);

end JK_tr;
architecture JK_tr of JK_tr is

      begin
      process(clk, reset) is
      variable Qint: STD_LOGIC;
      begin
      if (reset ='0') then Qint:='0';
      elsif (CLK'event and CLK ='1') then
      if (J='1' and K='1') then Qint := not(Qint);
      elsif (J='0' and K='0') then Qint:=Qint;
      elsif (J='1' and K='0') then Qint:='1';
      elsif (J='0' and K='1') then Qint:='0';
      end if; end if;
      Q<=Qint;
      end process;

end JK_tr;

[Kuzmi4 0]

2 Maverick

вот так, по вашей вине, ещё один не научился пользоваться гуглом...