[gosha 0]

Здравствуйте.

 

Не совсем понятно по .ucf:

 

На плате Virtex_5 (ML_507), pci_express endpoint

tx+-/rx+-, clk+- подключены на GTX_DUAL_X0Y1

 

CONFIG PART = xc5vfx70t-ff1136-1;
NET  "sys_clk_p"       LOC = "AF4";
NET  "sys_clk_n"       LOC = "AF3";
INST "refclk_ibuf"     DIFF_TERM = "TRUE";
INST "ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTX_DUAL_X0Y1;
INST "ep/pcie_ep0/pcie_blk/pcie_ep"                       LOC = PCIE_X0Y1;

 

 

 

При сборке этого выдает ошибку:

ERROR:PhysDesignRules:2270 - Block

ep/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i (GTX_DUAL_X0Y1) needs

GTX_DUAL_X0Y2 instantiated: When using a GTP/GTX with a REFCLK coming from an

IBUFDS element near another GTP/GTX and forwarding that clock using dedicated

routing, each GTP in between the source and destination must be instantiated

in the correct manner (See AR 33473). If you don't instantiate these other

GTP tiles the software tools will route the REFCLK correctly, but the design

may not work in hardware.

ERROR:PhysDesignRules:1859 - The computed value for the VCO operating frequency

of PLL_ADV instance ep/pcie_ep0/pcie_blk/clocking_i/use_pll.pll_adv_i is

calculated to be 1250.000000 MHz. This falls above the operating range of the

PLL VCO frequency for this device of 400.000000 - 1000.000000 MHz. Please

adjust either the input frequency CLKIN_PERIOD, multiplication factor

CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to achieve a VCO

frequency within the rated operating range for this device.

ERROR:Pack:1642 - Errors in physical DRC.

 

Что я делаю не так ?

 

/*===========================================================*/

 

Зачем указывать constrain:

INST "ep/pcie_ep0/pcie_blk/pcie_ep" LOC = PCIE_X0Y1;

Если в Virtex-5 FPGA RocketIO GTP Transceiver User Guide UG196 на блок-схеме стр 26 PCI Express Block в GTP_DUALColumn не входит.

 

 

Заранее спасибо.