Есть файл реализации функции девайса. Когда смотрю часовые диаграмы - то все нормально. Но когда делаю testbench и реализую там девайс как компонент, то при попытке инициализировать симуляцыю, появляется ошибка :: # Signal RGZ not found in design, где RGZ внутренний сигналь реализации компонента. Пока даже преподаватели не могут обьяснить, почему.
Помогите если кто знает???!!!
Я там добавил файли, если єто поможет
Реализация компонента:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity SpecializedDevice is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
CX : in STD_LOGIC;
CY : in STD_LOGIC;
EZ : in STD_LOGIC;
DIO : inout STD_LOGIC_VECTOR(7 downto 0);
RDY : out STD_LOGIC
);
end SpecializedDevice;
--}} End of automatically maintained section
architecture SpecializedDevice of SpecializedDevice is
type SummBits is array (7 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
type SummBitsSmall is array (3 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal RGY: STD_LOGIC_VECTOR(7 downto 0);
signal RGX: STD_LOGIC_VECTOR(7 downto 0);
signal RGZ: STD_LOGIC_VECTOR(7 downto 0);
signal RGXT: STD_LOGIC_VECTOR(7 downto 0);
signal RGYT: STD_LOGIC_VECTOR(7 downto 0);
begin
RGXP: process(CLK,RST)
begin
if RST='1' then RGX<="00000000";
elsif CLK'event and CLK='1' and CLK'last_value='0'and CX='0' then RGX<=DIO;
end if;
end process RGXP;
............
.
.
end
Реализация testbench
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity testbench is
end testbench;
--}} End of automatically maintained section
architecture TestBenchArch of testbench is
signal Data: std_logic_vector(7 downto 0);
signal Reset,EX,EY,Enable_Z,Ready:std_logic;
signal Clock: std_logic:='1';
component SpecializedDevice is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
CX : in STD_LOGIC;
CY : in STD_LOGIC;
EZ : in STD_LOGIC;
DIO : inout STD_LOGIC_VECTOR(7 downto 0);
RDY : out STD_LOGIC
);
end component SpecializedDevice;
begin
UUT:
component SpecializedDevice
port map (
RST => Reset,
CLK => Clock,
CX => EX,
CY => EY,
EZ => Enable_Z,
DIO =>Data,
RDY =>Ready
);
Generate_pins:
process
begin
-- Testing X=2 Y=3
Enable_Z <='1'; EX <= '1'; EY<='1';
Reset <= '1';
wait for 30 ns;
Reset <= '0';
Data <= "00000010";
EX <= '0'; wait for 30 ns;
EX <= '1';
Data <= "00000011";
Ready<='0';
EY <= '0'; wait for 30 ns;
EY <= '1';
Data <= "ZZZZZZZZ";
wait for 350 ns;
Ready<='1';
Enable_Z <='0';
wait for 30 ns;
Enable_Z <= '1';
wait for 30 ns;
end process;
clock_rate:
process
begin
Clock <= not Clock;
wait for 20 ns;
end process;
-- enter your statements here --
end architecture TestBenchArch;
Делаю Simulation\\Initialize Simulation
Ошибки:
# Signal RGYT not found in design
# Signal RGXT not found in design
# Signal RGX not found in design
# Signal RGY not found in design
# Signal SummSecond not found in design
# Signal SummThird not found in design
# Signal forth not found in design
# Signal carry not found in design
# Signal Second1 not found in design
# Signal Second2 not found in design
# Signal Second3 not found in design
# Signal Third1 not found in design
# Signal Third2 not found in design
# Signal RGZ not found in design
# Signal Third3 not found in design
# Signal step not found in design
src.zip
