[colombo_2007 0]

Задача стоит такая – изучить интерфейс ATA для дальнейшего использования в разработках. Сейчас в этих целях леплю COM->IDE.

Это предыстория, а вопрос такой:

В описании стандарта ATA написано

6.2.7 Device/Head register

This register contains device addressing and sector addressing information.

7 6 5 4 3 2 1 0

r L r DEV HS3 HS2 HS1 HS0

· Bit 7 is reserved;

· L is the sector address mode select. When the L bit is equal to zero, addressing is by CHS mode.

When the L bit is equal to one, addressing is by LBA mode;

· Bit 5 is reserved;

· DEV is the device address. When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit

is equal to one, Device 1 is selected;

· If the L bit is equal to zero (CHS Mode), the HS3 through HS0 bits contain the head address of the CHS

address. The HS3 bit is the most significant bit. If the L bit is equal to one (LBA Mode), the HS3 through

HS0 bits contain bits 27 through 24 of the LBA. This field shall be updated to reflect the media address of

the error when a media access command is unsuccessfully completed.

 

В описании модели в Proteus:

Drive address register

7 6 5 4 3 2 1 0

High Z nWGT nHS3 nHS2 nHS1 nHS0 nDS1 NDS0

Bit Mnemonic Name Description

0 nDS0 Not drive selected 0 When zero, the master drive is selected.

1 nDS1 Not drive selected 1 When zero, the slave drive is selected.

2 nHS0 Not head selected The inverse of the currently selected head, for example, (where nHS0 is the LSB,) 1101b is head 2.

3 nHS1

4 nHS2

5 nHS3

6 nWGT Not write gate Indicates when writing to the drive is in progress.

 

 

Где правда и как это понимать?