Armen

smotri: http://forum.electronix.ru/index.php?showtopic=3297

Kontroller u 5502 ochen neudachniy, posle kajdogo dostupa k pamyati on v srednem tratit 13-18 ciklov (tochnoi ne pomnyu) EMIF-a pered sleduyushim dostupom, vse zavisit ot konkretnoy chastoti i ot tipa dostupa (read/write, byte/sjort/long access). Tak naebolee udachnaya kanfiguracia eto kompirovanie is SDRAMA bloka dannix kotoriy ti sobiraeshsya ispolzovat v internal memory a ispolzuya DMA a zatem obratno. Dlya max proizvoditelnosti DMA (burst mode), bolee konkretno kakie zaderjki u 5502 EMIF-a chitay doc na sayte TX spra924a.pdf. Zdes v forume mi uje razok obsujdali vse eti nastroyki.... so vsemi znacheniyami prosmotri history.

ok

Ok ponyatno. Ti pravilno skonfiguriroval registri IER0 i IER1? Mojet u tebya prerivanie prixodit ( mojesh proverit po regitram IFR0, IFR1 ) No oni zamaskirovani IER0 ili IER1, poetomu i interrupta ne voznikaet.

FIFO u tebya kakoe to otdelnoe ustroystvo?

Etogo dumayu net, on poka chto v principe nevenkiy... V lyubom sluchae luchshe ego rodnie.

dlya chego nujen interrupt ot FIFO. V principe interrupt zaversheniya DMA vpolne dostatochen. Mojet ya zadachu ne vpolne korrektno predstavlyayu? <_<

Skoree vsego OC budet no otkompilirovanniy... polzi malovato... xotya .... Kstati mne nujna os dlya StarCore... iz za nedostupnosti vsego i platnosti reshil sam napisat... Kak trenirovku pereklyuchenie zadach realizoval na 5510.. vrode idei rabotayut...

a kak ideya samim napisat'????

poprobuy eti nastroyki kstati u tebya ved DMA copy, okonchanie processa copy mojno uznat po interruptu #define DMACSDP_DSTBEN_DISABLED (0 << 14) #define DMACSDP_DSTBEN_ENABLED (2 << 14) #define DMACSDP_DSTPACK_DISABLED (0 << 13) #define DMACSDP_DSTPACK_ENABLED (1 << 13) #define DMACSDP_DST_DARAM0 (0 << 9) #define DMACSDP_DST_DARAM1 (1 << 9) #define DMACSDP_DST_EMIF (2 << 9) #define DMACSDP_DST_PEREPH (3 << 9) #define DMACSDP_SRCBEN_DISABLED (0 << 7) #define DMACSDP_SRCBEN_ENABLED (2 << 7) #define DMACSDP_SRCPACK_DISABLED (0 << 6) #define DMACSDP_SRCPACK_ENABLED (1 << 6) #define DMACSDP_SRC_DARAM0 (0 << 2) #define DMACSDP_SRC_DARAM1 (1 << 2) #define DMACSDP_SRC_EMIF (2 << 2) #define DMACSDP_SRC_PEREPH (3 << 2) #define DMACSDP_DATATYPE_8BIT (0 << 0) #define DMACSDP_DATATYPE_16BIT (1 << 0) #define DMACSDP_DATATYPE_32BIT (2 << 0) //CHANNEL #1 REGISTERS #define DMA_CSDP1_0C20 0x0C20 #define DMA_CCR1_0C21 0x0C21 #define DMA_CICR1_0C22 0x0C22 #define DMA_CSR1_0C23 0x0C23 #define DMA_CSSA_L1_0C24 0x0C24 #define DMA_CSSA_U1_0C25 0x0C25 #define DMA_CDSA_L1_0C26 0x0C26 #define DMA_CDSA_U1_0C27 0x0C27 #define DMA_CEN1_0C28 0x0C28 #define DMA_CFN1_0C29 0x0C29 #define DMA_CSFI1_0C2A 0x0C2A #define DMA_CSEI1_0C2B 0x0C2B #define DMA_CSAC1_0C2C 0x0C2C #define DMA_CDAC1_0C2D 0x0C2D #define DMA_CDEI1_0C2E 0x0C2E #define DMA_CDFI1_0C2F 0x0C2F #define IO_PORT(a) (*( (ioport unsigned short*)(a))) void memcpyDMAInit() { //DMA receive port configuration for background memory copy //CHANNEL #1 REGISTERS IO_PORT(DMA_CFN1_0C29) = 1; IO_PORT(DMA_CICR1_0C22) = 0x0008; IO_PORT(DMA_CSFI1_0C2A) = 0x0000; IO_PORT(DMA_CSEI1_0C2B) = 0x0000; IO_PORT(DMA_CSAC1_0C2C) = 0x0000; IO_PORT(DMA_CDAC1_0C2D) = 0x0000; IO_PORT(DMA_CDEI1_0C2E) = 0x0000; IO_PORT(DMA_CDFI1_0C2F) = 0x0000; } void memcpyDMA( void *pDst, void *pSrc, short size ) { short CSDP; IO_PORT(DMA_CCR1_0C21) = 0x0000; IO_PORT(DMA_CSSA_L1_0C24) = BYTE_ADDR_LO(pSrc); IO_PORT(DMA_CSSA_U1_0C25) = BYTE_ADDR_HI(pSrc); IO_PORT(DMA_CDSA_L1_0C26) = BYTE_ADDR_LO(pDst); IO_PORT(DMA_CDSA_U1_0C27) = BYTE_ADDR_HI(pDst); IO_PORT(DMA_CEN1_0C28) = size; CSDP = DMACSDP_DATATYPE_16BIT | DMACSDP_DSTBEN_ENABLED | DMACSDP_DSTPACK_ENABLED | DMACSDP_SRCBEN_ENABLED | DMACSDP_SRCPACK_ENABLED; if( ((unsigned long)pDst) >> 15 == 0 ) CSDP |= DMACSDP_DST_DARAM1; else CSDP |= DMACSDP_DST_EMIF; if( ((unsigned long)pSrc) >> 15 == 0 ) CSDP |= DMACSDP_SRC_DARAM0; else CSDP |= DMACSDP_SRC_EMIF; IO_PORT(DMA_CSDP1_0C20) = CSDP; IO_PORT(DMA_CCR1_0C21) = 0x50c0; }

Reshenie naydeno, nedokumentirovannaya opciya kompilyatora. Esli komu nibud ponadobitsya obrashaytes.

EMIF u 5510 serii znachitelno luchshe chem u 5502/5501, tam ogromnaya raznica po skoroti dostupa k pamyati. Esli ti prosmotrel link to tam na poslednix stranicax privedeni skorosti dostupov k pamyati u 5502 i est sravnenie s 5510. Tormoz zdes imenno v EMIFe. Zadacha ponyatna. Da imeet znachenie chto ti chitaesh i chto pishesh, skajem esli ti chitaesh iz pamyati short i long (16 bit, 32 bita) to skorost u tebya budet odinakowoy, t.e. esli u tebya copy masivov to luchshe delat kak long (MOV dbl(*AR0), ...), viigrivaesh v dva raza. Emif ustroen takim obrazom chto esli ti osushestvlyaesh 16 bitniy dostup, to on vse ravno k pamyati osushestvlyaetsya 32 bitniy dostup i chitaet srazu 32 bita a ne 16. Esli u tebya time kritichnie bloki (skajem vocoderi), to luchshe dannie peretashit v internal memory, tam s nimi rabotat a zatem obratno v external. poskolku cherez processor obrashenie k pamyati vsegda odinochnoe to prosto kommandami tipa mov uvelichit skorost k pamyati nelzya, zato eto mojno sdelat pri pomoshi DMA. pri vernix nastroykax DMA osushestvlyaet burst dostup k pamyati. Chto minimum v dva raza bistree chem prosto mov dbl(*ARx),... Pri pomoshi DMA mojno dobitsya prilichnix skorostey. Vobshet tut nujno sdelat chto vrode programnogo keshirovaniya. Da i eshe ne zabud' pro nastroyku skorosti sistemnix clocko-ov, otkuda beryet clock tvoy emif(3). Tam po defaultu delitel po moemu 4 t.e. esli core clock 200 MHz emiv->50 . Postav delitel na 2.... (100MHz emif).

Privet. Tut delo ne v nastroykax, a v tom chto sam emif imeet ochen nizkuyu proizvoditelnost. Daje pri vernix nastroykax burst u nego 2X32. vot tebe siilka: http://focus.ti.com/docs/apps/catalog/reso...ctName=spra924a zdes naydesh vse otveti po teme proizvoditelnosti emifa i cache. Ya sam namuchalsya, pravda u menya SDRAM no vobshem eto dela ne menyaet. Vse vozmojnie testi i proverki proizvedeni, kstati kak info... u 5501 toje 32-x bitniy emif

vot nebolshaya ssilochka po RTOSam kak platnim tak i ne ochen, ~25-30 stuk :) http://www.cs.aau.dk/~mixxel/cisslab/os_in...nfo.php#VxWorks

То, что адрес переменной align 4 - так и должно быть с 32-битными переменными. С 16-битными - получится сделать align 2, с 8-битными - align 1. С 64-битными - align 8 будет. И, соответственно, кратен 4 размер всех структур - они-же 32-битные. По другому, ни как, вернее как, но вручную, на ассемблере + еще собирать по кусочкам 32-битные переменные. Т.е. иначе скорости у вас не выйдет. А какие проблемы у вас с этим? В память не помещаетесь? <{POST_SNAPBACK}> Da no u menya kak raz ne 32 bitnie peremennie, struktura soderjit pole razmerom v odin byte: struct { char a; } z; compilyator pri kompilyacii delaet razmer structuri z 4 byte i align to 4, xotya tam maksimalniy fundamentalniy tip 8 bit. no na drugix kompilyatorax vse ok skajem ot Green Hills. Zadacha takaya, ot chipa 91c111 prixodit ethernet paket kotoriy postupayet v TCP/IP stek, stek gotov... no iz za togo chto compiler delaet vse strukturi align to 4 i razmer vsex struktur kraten 4 proisxodit smeshenie poley vsex struktur... menyat realizaciyu ne ochen pravilno... ili ya chto to nedoglyadel v opciyax compilera ili je compiler ne verno rabotaet i ne sootvetstvuet ego je documentacii. <_<