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nand_gates

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  1. Refer to The Complete Digital design Book. for parallel CRC calculations concept! Complete Digital Design Mark Bloch
  2. Check this out! :laughing: module bin2bcd(/*AUTOARG*/ // Outputs S, // Inputs A ); input [3:0] A; output [3:0] S; reg [3:0] S; always @(A) case(A)//synopsys parallel_case 0 : S=0; 1 : S=1; 2 : S=2; 3 : S=3; 4 : S=4; 5 : S=8; 6 : S=9; 7 : S=10; 8 : S=11; 9 : S=12; default : S=4'bxxxx; endcase endmodule // bin2bcd module Binary_to_BCD_8(P,B); output [9:0] P; //BCD form of B input [7:0] B; wire [3:0] co1, co2, co3, co4; wire [2:0] co6; assign P[0]= B[0]; bin2bcd C1(.A({1'b0,B[7:5]}), .S(co1)); bin2bcd C2(.A({co1[2:0],B[4]}), .S(co2)); bin2bcd C3(.A({co2[2:0],B[3]}), .S(co3)); bin2bcd C4(.A({co3[2:0],B[2]}), .S(co4)); bin2bcd C5(.A({co4[2:0],B[1]}), .S(P[4:1])); bin2bcd C6(.A({1'b0,co1[3],co2[3],co3[3]}), .S({P[9],co6})); bin2bcd C7(.A({co6,co4[3]}), .S(P[8:5])); endmodule // Binary_to_BCD_8 module test(); reg [7:0] B; wire [9:0] P; // End of automatics Binary_to_BCD_8 Binary_to_BCD_8(/*AUTOINST*/ // Outputs .P (P[9:0]), // Inputs .B (B[7:0])); initial begin $monitor($time,,"Bin=%0x BCD = %0x",B,P); B=0; repeat(256) #10 B=B+1; $finish; end endmodule // test
  3. I am using Modelsim 10.4 (64bit) on Windows 8.0 (64bit). No need for any perticular example. Simple counter verilog code is sufficient! Only thing is set VoptFlow = 1 in modelsim.ini file. No licensing issue! May be some OS protection issue!!?? :smile3046:
  4. There is no issue with the work lib. I use the commands as follows.. vlib work vcom counter.v counter_tb.v vsim counter_tb The problem I am talking about is with the setting in modelsim.ini file. When I set VoptFlow = 1 in this file and run my design using above commands I get the Error ** Fatal: Internal Error - vopt returned success but vsim could not find a design to simulate!. Thanks :smile3046:
  5. I am running modelsim(64bit) 10.4 on windows64 8.0 [vsim] ; vopt flow ; Set to turn on automatic optimization of a design. ; Default is on VoptFlow = 1 With this set in modelsim.ini file I am getting following error while running vsim command. ** Fatal: Internal Error - vopt returned success but vsim could not find a design to simulate!. Please contact customer support for further assistance. With VoptFlow = 0 no error! How to fix this problem? Also I keep on getting could not find interpreter "ScintillaTk" Error
  6. After some efforts I was able to get the windows mwssageBox using verilog DPI... Here goes the code! Still I am very far from my target :smile3046: win32api_msimDPI.rar
  7. I tried it no luck! The problem is you can't call win32apis outside WinMain !! It will be great if you can give some example! Thanks :smile3046:
  8. Here how I have done with modelsim tcl. Its very slow! I want to do it with calling win32 API's through systemverilog DPI . :smile3046: vgatest.rar
  9. thanks I have volume 3 I am want volume 1. I think they are different!
  10. Hi Friends, I am looking for Digital Signal Processing Applications with the TMS320 Family Vol.1 https://www.amazon.com/Digital-Processing-A...s/dp/0132124661 Thanks!
  11. Is it possible to call win32api using Systemverilog DPI? I want to simulate VGA screen using modelsim with SystemVerilog code! :smile3046:
  12. One simple way! module test(); integer i,j, mcd,number; integer array[0:100]; initial begin mcd = $fopen("ver.txt","r"); i=0; while (!$feof(mcd)) begin $fscanf(mcd, "%0d\n",number); array[i] = number+1; i=i+1; end $fclose(mcd); mcd = $fopen("ver.txt","w"); for (j=0;j<i;j=j+1) begin $fwrite (mcd,"%0d\n",array[j]); end $fclose(mcd); end // initial begin endmodule
  13. Check this out! integer mcd,number; initial begin mcd = $fopen("ver.txt","a"); begin number = 1; $fwrite (mcd,"%d \n",number); end $fclose(mcd); end
  14. In verilog components can be instantiated just like data types! Use generate with VHDL architecture GEN of FIFO_BANK is component fifo32k_by_1 port (rst, din, wrclk, wren, rdclk, rden: in std_ulogic; rlsb, dout : out std_ulogic); begin GEN_fifo32k_by_26: for I in 25 downto 0 generate fifo32k_by_1_X : fifo32k_by_1 port map rst(rst), din(din(I)), wrclk(wrclk), wren(wren), rdclk(rdclk), rden(rden), rlsb(rlsb), dout(d_out(I))); end generate fifo32k_by_26; end GEN;
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