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unexpected PROCESS

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Имеется следующий код на VHDL:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

.........


entity d_trigger is
    Port ( clk  : in   STD_LOGIC;
           q : in   STD_LOGIC;
           clk_out : out  STD_LOGIC);
end d_trigger;

architecture Behavioral of d_trigger is
process (clk)
begin
   if clk'event and clk='1' then
    q<=clk_out;
   end if;
end process;
end Behavioral;

 

Появляется ошибка:

parse error, unexpected PROCESS

 

Не могу понять как её исправить :smile3046:

 

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

.........


entity d_trigger is
    Port ( clk  : in   STD_LOGIC;
           q : in   STD_LOGIC;
           clk_out : out  STD_LOGIC);
end d_trigger;

architecture Behavioral of d_trigger is
begin -- !!!
process (clk)
begin
   if clk'event and clk='1' then
    q<=clk_out;
   end if;
end process;
end Behavioral;

Вот где !!!, кажется этой строки недостает.

Edited by yume

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