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Подключения в VHDL

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Привет !


Вопрос следующий:



signal one : std_logic_vector ( 3 downto 0);

signal two : std_logic_vector ( 3 downto 0);



one (3 downto 0) <= two (0 to 3);


Получается реализовать только как

one(3) <= two(0);

one(2) <= two(1);

и т д.

Наверное должно получится с использованием FOR .. GENERATE если, например, шина большая



А может есть способ проще?

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