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Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation link


Вроде бы на сайте еще не мелькала :)


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FPGA-based Implementation of Signal Processing Systems link


ЗЫ: За последние несколько лет вышло достаточное количество книг в направлении СнК. Нуна будет прошурстить по свободе данную "почву" :)


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Случайно не у кого нет книги в электроне Proceedings of the 2011 International Conference on Informatics, Cybernetics, and Computer Engineering (ICCE2011). Наткнулся на в интернете на пару страниц с книги, заинтересовало. Пытался найти выдает только платные

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Для изучения VHDL очень помогла эта книга. Может кому-то тоже пригодится.

А вообще, у каждого разработчика где-то есть своя большая библиотека на интересующую тему. Всё что сам нашёл в интернете и что дали наставники :rolleyes:



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Гуляя по сети наткнулся на неплохую выжимку с вебинара по видеообработке на чипах Altera.

Ссылка : http://www.eewebinar.co.kr/video/121120_al...webinar1120.pdf

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Download the latest FREE eBook version of the System-on-Chip Design with Arm Cortex-M Processors Reference Book


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На генезисе 114 книжек по теме FPGA http://gen.lib.rus.ec/search.php?&req=FPGA&phrase=1&view=simple&column=def&sort=def&sortmode=ASC&page=1

По Xilinx выдает еще 30 штук, из которых часть на русском.

Edited by fguy

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Попалась забавная книга с исходниками на verilog от Altera. Advanced Synthesis Cookbook. Исходники.


Под спойлером оглавление:


Chapter 1.  Introduction
Blocks and Techniques 
Simulating the Examples
Using a C Compiler

Chapter 2.  Arithmetic
Basic Addition
Ternary Addition
Grouping Ternary Adders
Combinational Adders
Double Addsub/ Basic Addsub
  Two’s Complement Arithmetic Review
  Traditional ADDSUB Unit
Compressors (Carry Save Adders)
  Compressor Width 6:3
  Compressor Width 3:2
  Compressor Width 12:4
  Compressor Width 36:6
  Compressor Width 64:7
  Combining Compressors (Compressor Width 4:2)
Bit Population Count
Splitting Adder Chains
Pipelined Adder Chains
Carry Select Adders
Adder Trees
Basic Multiplication
Multiplication With Rotate and Shift Modes
High-Speed LCell-Based Multiplication
Multiplication of Large Integers (Karatsuba Algorithm)
Division (Unsigned Integer)

Chapter 3.  Floating Point Tricks
Floating Point to Fixed Point Conversion
Approximate Square Root
Approximate Inverse Square Root
Approximate Floating Point Divide (Single Precision)

Chapter 4.  Translation and Format Conversion
One-Hot Decoder (Binary to One-Hot)
One-Hot to Binary
Mask Generation
Binary-to-Gray Conversion
Gray-To-Binary Conversion
Seven Segment Display Driver
Binary-to-ASCII Hexadecimal Conversion
ASCII to 32 Character Liquid Crystal Display (LCD)
ASCII Hexadecimal-to-Binary Conversion
Binary-to-Decimal/Binary-Coded Decimal Adders

Chapter 5.  Video
YCbCr (4:4:4) to RGB Conversion
RGB to Hue Conversion
Sum of Absolute Difference (SAD)
VGA Monitor Control
Character Display

Chapter 6.  Arbitration
Bitscan (Priority Masking)
Arbiters with Fairness
Priority Encoding
Channel Arbiter

Chapter 7.  Multiplexing
Basic Multiplexing (Binary Encoded)
Decode/Select Multiplexing
If/Else Multiplexing (?: Multiplexing)
Priority Multiplexing
8-to-1 Multiplex Building Blocks
Barrel Shift
Use of Register Secondary Signals for Multiplexing
Bus Multiplexing
Pipelined Bus Multiplexing
Word Muxing 20:5
Word Muxing 20:8

Chapter 8.  Comparison and Adder Detection
Bus Equality ( A == B )
Mapping Wide Single-Output Functions to the Carry Chain
Equal to Constant
Less than Constant
Address in Range Comparison (LOWER <= addr < UPPER)
Match or Inverse Match
Min and Max / Variable Sign Comparison

Chapter 9.  Storage
Register Banks
24-Bit/16-Bit Stream Buffers (RGB/Memory Buffer)
RAM-Based Shift Register
RAM-Based Shift Register (MLAB Variant)   
FIFO (Dual Clock)
Dual Clock FIFO (MLAB Variant)   
Simple Quad Port RAM
Ternary Content Addressable Memory (TCAM)
  Register-Based Ternary CAM
  RAM-Based Ternary CAM
Backpressure Skid Buffer
Register Based Buffer FIFO

Chapter 10.  Counters
Basic Binary Counter
Up/Down Counter
Seconds Timer
System Timer
Modulus Counter with Lookahead
Basic Gray Counter and Gray Lookahead

Chapter 11.  Communication
8B10B Encoder/ Decoder
Chaining 8B10B coders
Universal Asynchronous Receiver Transmitter (UART)
Interface to Parallax Global Positioning
System (GPS) Receiver
  TX Lane Implementation
    64/67-Bit Encoding
    Interlaken Scrambler
    Framing schedule
  RX Lane Implementation
    Word Alignment
    Decode 67/64
    Framing schedule
  Lane Test Environment

Chapter 12.  Cyclic Redundancy Check
CRC XOR Decomposition
CRC-16 Fixed Data Width
CRC-24 Fixed Width
CRC-32 Fixed Data Width
CRC-32C (Castagnoli) Fixed Width
CRC-32 Variable Data Width (Residues)
CRC-32 Ethernet FCS
CRC Decomposition and Pipeline

Chapter 13.  Error Correction Codes
64/72-Bit ECC Encoder/ Decoder
64/72-Bit ECC Dual-Port Internal RAM
ECC 32/39-Bit Variation
ECC 16/22-Bit Variation
ECC 8/13-Bit Variation
ECC 2/6-Bit Variation
Reed-Solomon Forward Error Correction (FEC)
  Reed-Solomon Transmitter
  Reed-Solomon Receiver
  Galois Field Multiplication

Chapter 14.  Random and Pseudorandom Functions
Linear Feedback Shift Register
Built-In Logic Block Observer
C Library Random Number Generator
True Random Numbers
  Race Condition-Based True Random Numbers
Word Stream Scrambling

Chapter 15.  Cryptography
Data Encryption Standard
Triple DES
UNIX Password Encryption
Advanced Encryption Standard/ Rijndael
  The Rijndael S-BOX/sub_bytes
  Rijndael shift_rows
  Rijndael mix_columns and Round Keying
  Rijndael Key Evolution
  Rijndael 128 Encipher
  Rijndael 128 Decipher
  Rijndael 256-Bit Key Size (AES 256)
  Rijndael 192-Bit Key Size (AES 192)
RC4 Stream
Secure Hash Algorithm

Chapter 16.  Synchronization
System Reset Control
Clock Multiplexing
Synchronizer Chain

Chapter 17.  Debugging
Temperature Sensor
Frequency Monitor
JTAG To C Probe



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