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Какая особенность? Сорцы CoreLib доступны: $XILINX/vhdl/src/XilinxCoreLib. Но эта библиотека симуляционная. Её можно посмотреть, но толку от этого мало. В ней в полный рост используется несинтезируемое подмножество VHDL.

 

Честно говоря, я не знаю, что хочет уважаемый Maverick) Ему уже дали три синтезируемых делителя, посоветовали взять блок из Coregen, ему все мало ;) Поэтому уж от безысходности пришлось давать все описания делителей, о которых знал, в т.ч. несинтезируемые :biggrin:

 

Шутка. В реальности же, исходники CoreLib лишь слегка просматривал, но не знал, что код, содержащийся в них несинтезируемый. Не было случая проверить.

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try this:

 

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_signed.all;

use ieee.std_logic_arith.all;

 

entity divide is

port (

clk : in std_logic;

sign : in std_logic;

divider : in std_logic_vector(31 downto 0);

dividend : in std_logic_vector(31 downto 0);

reminder : out std_logic_vector(31 downto 0);

quotient : out std_logic_vector(31 downto 0);

ready : out std_logic

);

end divide;

 

architecture div of divide is

constant Z32 : std_logic_vector(31 downto 0) := (others => '0');

constant Z31 : std_logic_vector(30 downto 0) := (others => '0');

signal QuotientReg, QuotientTemp : std_logic_vector(31 downto 0);

signal Difference, DividendCopy, DividerCopy : std_logic_vector(63 downto 0);

signal ready_internal : std_logic;

signal BitReg : integer range 0 to 63 := 0;

signal NegativeOutput : std_logic := '0';

 

function shl(ARG: std_logic_vector) return std_logic_vector is

variable ARG_length: INTEGER := ARG'length-1;

variable result : std_logic_vector(ARG_length downto 0);

begin

result := ARG(ARG_length-1 downto 0) & '0';

return result;

end function;

 

function shr(ARG: std_logic_vector) return std_logic_vector is

variable ARG_length: INTEGER := ARG'length-1;

variable result: std_logic_vector(ARG_length downto 0);

begin

result := '0' & ARG(ARG_length downto 1);

return result;

end function;

 

function wnor(ARG: std_logic_vector) return std_logic is

variable input_len: INTEGER := ARG'length;

variable result,temp : std_logic := '0';

begin

for i in 0 to input_len-1 loop

temp := temp or arg(i) ;

end loop;

result := not temp;

return result;

end function;

 

begin

 

ready <= ready_internal;

quotient <= QuotientReg;

ready_internal <= wnor(conv_std_logic_vector(BitReg,6));

Reminder <= DividendCopy(31 downto 0) when (NegativeOutput = '0') else ((not DividendCopy(31 downto 0)) + '1');

 

process (clk,ready_internal,sign,BitReg)

begin

if (clk='1' and clk'event) then

if (ready_internal = '1') then

BitReg <= 32;

QuotientReg <= (others => '0');

QuotientTemp <= (others => '0');

if ( (sign = '0') or (dividend(31) = '0') ) then

DividendCopy <= Z32 & Dividend;

else

DividendCopy <= Z32 & ((not Dividend) + '1');

end if;

if ( (sign = '0') or (divider(31) = '0') ) then

DividerCopy <= '0' & Divider & Z31;

else

DividerCopy <= '0' & ((not Divider) + '1') & Z31;

end if;

NegativeOutput <= sign and ((divider(31) and not(dividend(31))) or (not(divider(31)) and dividend(31)) );

elsif (BitReg > 0) then

Difference <= DividendCopy - DividerCopy ;

QuotientTemp <= shl (QuotientTemp);

if (Difference(63) = '0') then

DividendCopy <= Difference;

QuotientTemp(0) <= '1' ;

end if;

if (NegativeOutput='0') then

QuotientReg <= QuotientTemp ;

else

QuotientReg <= (not QuotientTemp) + '1' ;

end if;

DividerCopy <= shr (DividerCopy);

BitReg <= BitReg - 1 ;

end if;

end if;

end process;

 

 

end div;

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