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gosha    0

gosha
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Just now, Jul'etta said:

я просто отдельно создала новый проект и поставила только это ядро. Ожидала какую угодно ошибку - но опять появилась та же.

1.png

Все- таки в License_manager что пишет по поводу лицензии на IP v_tpg ?

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Jul'etta    0

Jul'etta
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27 minutes ago, gosha said:

Все- таки в License_manager что пишет по поводу лицензии на IP v_tpg ?

подскажите, а на что надо обратить внимание?

 

12.jpg

Edited by Jul'etta

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RobFPGA    10

RobFPGA
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1 hour ago, Jul'etta said:

подскажите, а на что надо обратить внимание?

На сколько я понимаю  модуль   v_tpg  содержит в себе HLS ядро.  Которое должно  синтезироваться в HLS (и создать соответствующие файлы RTL) перед тем как пойдет синтез непосредственно RTL корки  и проекта целиком. 

Так  что в первую очередь надо смотреть лог синтеза.          

 

P.S. Вот как этот синтез  выглядит у меня (увы в версии 2021.1). 

Quote

...
source design_1_v_tpg_0_0.tcl -notrace
...

source ../Vitis_HLS/2021.1/scripts/vitis_hls/hls.tcl -notrace
INFO: Applying HLS Y2K22 patch v1.2 for IP revision
INFO: [HLS 200-10] Running '.../Vitis_HLS/2021.1/bin/unwrapped/lnx64.o/vitis_hls'

...

Sourcing Tcl script '.../vtg/project_1/project_1.runs/design_1_v_tpg_0_0_synth_1/runhls.tcl'
INFO: [HLS 200-1510] Running: open_project design_1_v_tpg_0_0 
INFO: [HLS 200-10] Creating and opening project '.../vtg/project_1/project_1.runs/design_1_v_tpg_0_0_synth_1/design_1_v_tpg_0_0'.
...

 


 

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RobFPGA    10

RobFPGA
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23 hours ago, Jul'etta said:

я прикрепила в первом посте этот файл, на который ругается. Лежит он на месте, никто его не трогал)

Ругается вам Vivado не на файл из первого поста, а на то что не найден модуль (design_Tx_for_ZC702_v_tpg_0_0_v_tpg ) который инстанцирован в этом файле. То есть либо этот файл (design_Tx_for_ZC702_v_tpg_0_0_v_tpg.v) не сгенерирован либо при его синтезе произошла ошибка (например из за отсутствия сгенерированных в HLS файлов). 

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Jul'etta    0

Jul'etta
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2 hours ago, RobFPGA said:

Ругается вам Vivado не на файл из первого поста, а на то что не найден модуль (design_Tx_for_ZC702_v_tpg_0_0_v_tpg ) который инстанцирован в этом файле. То есть либо этот файл (design_Tx_for_ZC702_v_tpg_0_0_v_tpg.v) не сгенерирован либо при его синтезе произошла ошибка (например из за отсутствия сгенерированных в HLS файлов). 

лог синтеза я прикрепляла выше, продублирую еще раз

 

 

*** Running vivado
    with args -log design_Tx_for_ZC702_v_tpg_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_Tx_for_ZC702_v_tpg_0_0.tcl


****** Vivado v2017.1 (64-bit)
  **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
  **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source design_Tx_for_ZC702_v_tpg_0_0.tcl -notrace
compile_c: Time (s): cpu = 00:00:01 ; elapsed = 00:06:18 . Memory (MB): peak = 311.258 ; gain = 5.566
config_ip_cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 313.285 ; gain = 2.027
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 389.176 ; gain = 75.891
INFO: [Synth 8-638] synthesizing module 'design_Tx_for_ZC702_v_tpg_0_0' [d:/Projects_Vivado/HDMI_Tx_design_for_ZC702/HDMI_Tx_design_for_ZC702.srcs/sources_1/bd/design_Tx_for_ZC702/ip/design_Tx_for_ZC702_v_tpg_0_0/synth/design_Tx_for_ZC702_v_tpg_0_0.v:57]
ERROR: [Synth 8-439] module 'design_Tx_for_ZC702_v_tpg_0_0_v_tpg' not found [d:/Projects_Vivado/HDMI_Tx_design_for_ZC702/HDMI_Tx_design_for_ZC702.srcs/sources_1/bd/design_Tx_for_ZC702/ip/design_Tx_for_ZC702_v_tpg_0_0/synth/design_Tx_for_ZC702_v_tpg_0_0.v:151]
ERROR: [Synth 8-285] failed synthesizing module 'design_Tx_for_ZC702_v_tpg_0_0' [d:/Projects_Vivado/HDMI_Tx_design_for_ZC702/HDMI_Tx_design_for_ZC702.srcs/sources_1/bd/design_Tx_for_ZC702/ip/design_Tx_for_ZC702_v_tpg_0_0/synth/design_Tx_for_ZC702_v_tpg_0_0.v:57]
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 429.242 ; gain = 115.957
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

 

 

 

задала вопрос в техподдержку Xilinx, посмотрю, что ответят. 

Edited by Jul'etta

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RobFPGA    10

RobFPGA
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2 hours ago, Jul'etta said:

лог синтеза я прикрепляла выше, продублирую еще раз

Я как раз и смотрю на этот лог (это лог синтеза проекта или ООС корки ?) и сравниваю  с тем файлом который вы в первом посте выложили (странный сдвиг номера строк на одну линию) 
 

Quote

Лог:   (информируют что начинают синтез  такого то модуля, который определен в таком то файле на такой то строке ) 
INFO: [Synth 8-638] synthesizing module 'design_Tx_for_ZC702_v_tpg_0_0' [d:/Projects_Vivado/HDMI_Tx_design_for_ZC702/HDMI_Tx_design_for_ZC702.srcs/sources_1/bd/design_Tx_for_ZC702/ip/design_Tx_for_ZC702_v_tpg_0_0/synth/design_Tx_for_ZC702_v_tpg_0_0.v:57]
Файл:
...
55 (* DowngradeIPIdentifiedWarnings = "yes" *)
56 module design_Tx_for_ZC702_v_tpg_0_0 (
57   s_axi_CTRL_AWADDR,
...

Лог:  (а это вопль что такой вот модуль, инстанцированный на такой то строке, не найден) 
ERROR: [Synth 8-439] module 'design_Tx_for_ZC702_v_tpg_0_0_v_tpg' not found [d:/Projects_Vivado/HDMI_Tx_design_for_ZC702/HDMI_Tx_design_for_ZC702.srcs/sources_1/bd/design_Tx_for_ZC702/ip/design_Tx_for_ZC702_v_tpg_0_0/synth/design_Tx_for_ZC702_v_tpg_0_0.v:151]

Файл:
...
147   design_Tx_for_ZC702_v_tpg_0_0_v_tpg #(
148     .C_S_AXI_CTRL_ADDR_WIDTH(8),
149     .C_S_AXI_CTRL_DATA_WIDTH(32)
150  ) inst (
151     .s_axi_CTRL_AWADDR(s_axi_CTRL_AWADDR),
...

Лог:  (мол шеф усе пропало и синтез этого модуля  не удался) 
ERROR: [Synth 8-285] failed synthesizing module 'design_Tx_for_ZC702_v_tpg_0_0' [d:/Projects_Vivado/HDMI_Tx_design_for_ZC702/HDMI_Tx_design_for_ZC702.srcs/sources_1/bd/design_Tx_for_ZC702/ip/design_Tx_for_ZC702_v_tpg_0_0/synth/design_Tx_for_ZC702_v_tpg_0_0.v:57]

Получается что этот файл (design_Tx_for_ZC702_v_tpg_0_0.v) виден для синтеза и синтезируется но с ошибкой,  так как вложенного в нем модуль  design_Tx_for_ZC702_v_tpg_0_0_v_tpg синтезатор найти не может.   
Но этот модуль design_Tx_for_ZC702_v_tpg_0_0_v_tpg это и есть топ для IP корки и обычно он синтезируется отдельно в режиме OOC (зависит от режима генерации BD  корки)

Нужно посмотреть полные логи генерации и OOC синтеза корки, либо попробовать поставить для вашего тестового BD режим синтеза global и тогда уж посмотреть лог синтеза всего проекта.   

 

P.S. Я  в свое время  добавил  хук на  стандартную команду  synth_design  чтобы  выводить список файлов которые включены в синтез при вызове этой команды.
Вот что получается если синтезировать тестовую BD с одной такой коркой  в Global mode  :scratch_one-s_head:

Spoiler
Quote

....
>> synth_design: list of source files ...
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
>> src: .../vtg/project_1/project_1.srcs/sources_1/bd/design_1/design_1.bd
>> src: .../vtg/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xci
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/sim/design_1_v_tpg_0_0.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/design_1_v_tpg_0_0.xdc
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/synth/design_1_v_tpg_0_0.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hls/hls_commands.txt
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/v_tpg_config.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/v_tpg.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/v_tpg_zoneplate.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls_video.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls_opencv.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_axi_io.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_arithm.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_core.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_fast.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_haar.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_harris.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_histogram.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_hough.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_imgbase.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_imgproc.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_io.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_mem.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_stereobm.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_types.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/src/hls/hls_video_undistort.h
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_am_addmul_16ns_1s_16ns_17_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_CTRL_s_axi.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_entry_proc.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_fifo_w8_d2_S.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_fifo_w16_d2_S.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_fifo_w24_d16_S.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_flow_control_loop_pipe_sequential_init.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_hls_deadlock_detection_unit.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_hls_deadlock_detector.vh
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_hls_deadlock_idx0_monitor.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_hls_deadlock_kernel_monitor_top.vh
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_hls_deadlock_report_unit.vh
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_8ns_6s_16s_16_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_8ns_7ns_13ns_15_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_8ns_7s_16s_16_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_8ns_8ns_15ns_16_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_8ns_8s_15ns_16_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_8ns_8s_16s_16_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mac_muladd_16s_16s_16ns_16_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mul_8ns_6ns_13_1_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_mul_mul_20s_8ns_28_4_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_MultiPixStream2AXIvideo.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_MultiPixStream2AXIvideo_Pipeline_VITIS_LOOP_937_2.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_reg_ap_uint_10_s.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_reg_int_s.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_reg_unsigned_short_s.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_regslice_both.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_bluYuv.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_bluYuv.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_grnYuv.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_grnYuv.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_redYuv.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_redYuv.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_tpgSinTableArray.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_tpgSinTableArray.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_tpgSinTableArray_9bit.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgBackground_Pipeline_VITIS_LOOP_521_2_tpgSinTableArray_9bit.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgForeground.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgForeground_Pipeline_VITIS_LOOP_730_2.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgForeground_Pipeline_VITIS_LOOP_730_2_whiYuv_2.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgForeground_Pipeline_VITIS_LOOP_730_2_whiYuv_2.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgBarSelYuv_u21.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgBarSelYuv_u21.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgBarSelYuv_v23.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgBarSelYuv_v23.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgBarSelYuv_y25.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgBarSelYuv_y25.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgCheckerBoardArray.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCheckerBoard_tpgCheckerBoardArray.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCrossHatch.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCrossHatch_blkYuv_1.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCrossHatch_blkYuv_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCrossHatch_whiYuv_1.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternCrossHatch_whiYuv_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarArray.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarArray.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_CEA_b.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_CEA_b.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_CEA_g.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_CEA_g.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_CEA_r.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_CEA_r.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_VESA_b.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_VESA_b.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_VESA_g.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_VESA_g.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_VESA_r.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelRgb_VESA_r.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_601_u.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_601_u.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_601_v.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_601_v.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_601_y.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_601_y.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_709_u.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_709_u.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_709_v.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_709_v.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_709_y.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternDPColorSquare_DPtpgBarSelYuv_709_y.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternTartanColorBars.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternTartanColorBars_tpgTartanBarArray.dat
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_tpgPatternTartanColorBars_tpgTartanBarArray.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_v_tpgHlsDataFlow.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/ip/design_1_v_tpg_0_0/hdl/verilog/design_1_v_tpg_0_0_v_tpg.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.v
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/design_1_ooc.xdc
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1.hwh
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/design_1.bda
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/hw_handoff/design_1_bd.tcl
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/synth/design_1.hwdef
>> src: .../vtg/project_1/project_1.gen/sources_1/bd/design_1/sim/design_1.protoinst
Command: ::synth_design_ -top design_1_wrapper -part xc7a35tftg256-1
Starting synth_design
...

 


 

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Jul'etta    0

Jul'etta
Posted · Report post
1 hour ago, RobFPGA said:

Я как раз и смотрю на этот лог (это лог синтеза проекта или ООС корки ?) и сравниваю  с тем файлом который вы в первом посте выложили (странный сдвиг номера строк на одну линию) 
 

Получается что этот файл (design_Tx_for_ZC702_v_tpg_0_0.v) виден для синтеза и синтезируется но с ошибкой,  так как вложенного в нем модуль  design_Tx_for_ZC702_v_tpg_0_0_v_tpg синтезатор найти не может.   
Но этот модуль design_Tx_for_ZC702_v_tpg_0_0_v_tpg это и есть топ для IP корки и обычно он синтезируется отдельно в режиме OOC (зависит от режима генерации BD  корки)

Нужно посмотреть полные логи генерации и OOC синтеза корки, либо попробовать поставить для вашего тестового BD режим синтеза global и тогда уж посмотреть лог синтеза всего проекта.   

 

P.S. Я  в свое время  добавил  хук на  стандартную команду  synth_design  чтобы  выводить список фалов которые включены в синтез при вызове этой команды.
Вот что получается если синтезировать тестовую BD с одной такой коркой  в Global mode  :scratch_one-s_head:

  Reveal hidden contents

 


 

огого... это лог синтеза всего проекта, а как отдельно отсинтезировать ядро? в отдельном проекте?

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RobFPGA    10

RobFPGA
Posted · Report post
1 minute ago, Jul'etta said:

огого... это лог синтеза всего проекта, а как отдельно отсинтезировать ядро? в отдельном проекте?

Если у вас  режим синтеза BD стоит в Out Of Context per IP (обычно это по умолчанию)  то лог синтеза корок на этой BD нужно смотреть выбрав в окне  Design Runs по иерархии вашу корку и открыв вкладку Log в окне Synthesis Run Properties.
Если лога не будет (например корка берется из кэша) то соответственно надо очистить кэш, ресетнуть BD и запустить генерацию и синтез BD снова.   

 

log.png

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gosha    0

gosha
Posted · Report post

Причем example design tpg собирается ok.

 

https://support.xilinx.com/s/question/0D52E00006hpt4HSAQ/video-test-pattern-generator-v-70-vivado-20173-cant-find-files-to-synthesize-?language=en_US

 

https://support.xilinx.com/s/question/0D52E00006hpkCvSAI/cant-synthesize-tpg-videosystem?language=en_US

 

https://support.xilinx.com/s/question/0D52E00006hpabeSAA/cant-synthesize-with-video-test-pattern-generator-even-with-license-get-module-not-found-error?language=en_US

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Jul'etta    0

Jul'etta
Posted (edited) · Report post

 

1 hour ago, gosha said:

В 19 vivado попробовал: аналогичная проблема

1.JPG

2.JPG

любопытная тенденция намечается

 

 

 

 

 

45 minutes ago, gosha said:

Причем example design tpg собирается ok.

 

https://support.xilinx.com/s/question/0D52E00006hpt4HSAQ/video-test-pattern-generator-v-70-vivado-20173-cant-find-files-to-synthesize-?language=en_US

 

https://support.xilinx.com/s/question/0D52E00006hpkCvSAI/cant-synthesize-tpg-videosystem?language=en_US

 

https://support.xilinx.com/s/question/0D52E00006hpabeSAA/cant-synthesize-with-video-test-pattern-generator-even-with-license-get-module-not-found-error?language=en_US

спасибо за ссылки! путь к файлу у меня около 120 символов (имею ввиду названия всех папок, с нижними подчеркиваниями и слэшами), т.е. вроде не очень длинный.

 

Edited by Jul'etta

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Jul'etta    0

Jul'etta
Posted (edited) · Report post
17 hours ago, RobFPGA said:

Если у вас  режим синтеза BD стоит в Out Of Context per IP (обычно это по умолчанию)  то лог синтеза корок на этой BD нужно смотреть выбрав в окне  Design Runs по иерархии вашу корку и открыв вкладку Log в окне Synthesis Run Properties.
Если лога не будет (например корка берется из кэша) то соответственно надо очистить кэш, ресетнуть BD и запустить генерацию и синтез BD снова.   

 

log.png

Есть! заодно научилась чистить кэш в виваде :) спасибо за инструкцию

 

Ниже скопировала лог:

*** Running vivado
    with args -log design_1_v_tpg_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_v_tpg_0_1.tcl


****** Vivado v2017.1 (64-bit)
  **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
  **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source design_1_v_tpg_0_1.tcl -notrace
compile_c: Time (s): cpu = 00:00:00 ; elapsed = 00:07:17 . Memory (MB): peak = 310.199 ; gain = 5.633
config_ip_cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 311.992 ; gain = 1.793
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 386.945 ; gain = 74.953
INFO: [Synth 8-638] synthesizing module 'design_1_v_tpg_0_1' [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:57]
ERROR: [Synth 8-439] module 'design_1_v_tpg_0_1_v_tpg' not found [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:151]
ERROR: [Synth 8-285] failed synthesizing module 'design_1_v_tpg_0_1' [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:57]
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 426.008 ; gain = 114.016
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

*** Running vivado
    with args -log design_1_v_tpg_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_v_tpg_0_1.tcl


****** Vivado v2017.1 (64-bit)
  **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
  **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source design_1_v_tpg_0_1.tcl -notrace

*** Running vivado
    with args -log design_1_v_tpg_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_v_tpg_0_1.tcl


****** Vivado v2017.1 (64-bit)
  **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
  **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source design_1_v_tpg_0_1.tcl -notrace
compile_c: Time (s): cpu = 00:00:00 ; elapsed = 00:06:37 . Memory (MB): peak = 310.758 ; gain = 5.633
config_ip_cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 312.184 ; gain = 1.426
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 386.668 ; gain = 74.484
INFO: [Synth 8-638] synthesizing module 'design_1_v_tpg_0_1' [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:57]
ERROR: [Synth 8-439] module 'design_1_v_tpg_0_1_v_tpg' not found [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:151]
ERROR: [Synth 8-285] failed synthesizing module 'design_1_v_tpg_0_1' [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:57]
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 425.730 ; gain = 113.547
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

*** Running vivado
    with args -log design_1_v_tpg_0_1.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source design_1_v_tpg_0_1.tcl


****** Vivado v2017.1 (64-bit)
  **** SW Build 1846317 on Fri Apr 14 18:55:03 MDT 2017
  **** IP Build 1846188 on Fri Apr 14 20:52:08 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source design_1_v_tpg_0_1.tcl -notrace
compile_c: Time (s): cpu = 00:00:00 ; elapsed = 00:06:33 . Memory (MB): peak = 310.578 ; gain = 5.637
config_ip_cache: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 311.805 ; gain = 1.227
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 387.387 ; gain = 75.582
INFO: [Synth 8-638] synthesizing module 'design_1_v_tpg_0_1' [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:57]
ERROR: [Synth 8-439] module 'design_1_v_tpg_0_1_v_tpg' not found [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:151]
ERROR: [Synth 8-285] failed synthesizing module 'design_1_v_tpg_0_1' [d:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/synth/design_1_v_tpg_0_1.v:57]
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 426.199 ; gain = 114.395
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

Edited by Jul'etta

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RobFPGA    10

RobFPGA
Posted · Report post
12 minutes ago, Jul'etta said:

Есть! заодно научилась чистить кэш в виваде :)

Ниже скопировала лог:

Чем дальше  тем непонятнее :scratch_one-s_head:Вроде  есть, а все тоже самое  :to_take_umbrage:
А можете  показать тут файл  design_1_v_tpg_0_1.tcl ?  Интересно посмотреть состав файлов для синтеза.  Заодно сможете проверить все ли фалы  из этого tcl  присутствуют на диске. 

 

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Jul'etta    0

Jul'etta
Posted · Report post
5 minutes ago, RobFPGA said:

Чем дальше  тем непонятнее :scratch_one-s_head:Вроде  есть, а все тоже самое  :to_take_umbrage:
А можете  показать тут файл  design_1_v_tpg_0_1.tcl ?  Интересно посмотреть состав файлов для синтеза.  Заодно сможете проверить все ли фалы  из этого tcl  присутствуют на диске. 

 

сейчас проверю файлы

design_1_v_tpg_0_1.tcl

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RobFPGA    10

RobFPGA
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Могу  предположить  что из этого скрипта  синтез HLS корки  выполняет вот эта команда  

compile_c [get_files D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1.xci]

И  судя  по всему  этот процесс не работает или  проходит с ошибкой. Можно  попробовать  выполнить этот скрипт  руками и  посмотреть что происходит  
Необязательно  выполнят все в скрипте, для начала достаточно  

# В консоле Vivado
file mkdir ./tmp_dir
file copy  D:/Projects_Vivado/test_v_tpg/test_v_tpg.srcs/sources_1/bd/design_1/ip/design_1_v_tpg_0_1/design_1_v_tpg_0_1.xci ./tmp_dir
create_project -in_memory -part xc7z020clg484-1

# В открывшемся новом окне Vivado  
read_ip ./tmp_dir/design_1_v_tpg_0_1.xci
generate_target all [get_files design_1_v_tpg_0_1.xci]
compile_c           [get_files design_1_v_tpg_0_1.xci]

И посмотреть что выдаст лог  для compile_c  

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