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Написать код Verilog - Мультиплексор 5-1. Предусмотреть защиту от неверного адреса

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On 5/2/2021 at 6:18 PM, store666 said:

жду предложений.


assign out = (sel == 3'd0)? in0 : (sel == 3'd1)? in1 : (sel == 3'd2)? in2 : (sel == 3'd3)? in3 : (sel == 3'd4)? in4 : (sel == 3'd5)? in5 : error; 


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02.05.2021 в 18:18, store666 сказал:

Написать код на Verilog для мультиплексора 5-1  и предусмотреть защиту от неверного адреса. жду предложений.

Поясните, что значит защита от неверного адреса.

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