Jump to content

    
Sign in to follow this  
Kiryanov

Проблемы с загрузкой petalinux на плате ZC706

Recommended Posts

День добрый всем!

При изучении embedded linux'а возникла очередная проблема. Совершенно не понятно откуда растут ее ноги. В общем я прогрузил нужный bsp ( xilinx-zc706-v2018.3-final.bsp ), и запустил на сборку. Не понятно, как его конфигурировать в некоторых деталях. Фигня получилась, что сначала не работала загрузка ядра, останавливалось все на boot - это исправляется так, как сказано здесь:

https://forums.xilinx.com/t5/Embedded-Linux/Zedboard-Unknown-command-booti-PetaLinux/td-p/899108

изменением booti на bootm в файле /<директория проекта>/project-spec/meta-plnx-generated/recipes-bsp/u-boot/configs/platform-auto.h.

После этого загрузка пошла, но останавливается на:

bootconsole [earlycon0] disabled  .

Привожу вывод из терминала

U-Boot 2018.01 (Mar 11 2021 - 13:54:32 +0000) Xilinx Zynq ZC706                 
                                                                                
Model: Zynq ZC706 Development Board                                             
Board: Xilinx Zynq                                                              
Silicon: v3.1                                                                   
I2C:   ready                                                                    
DRAM:  ECC disabled 1 GiB                                                       
MMC:   mmc@e0100000: 0 (SD)                                                     
SF: Detected s25fl128s_64k with page size 512 Bytes, erase size 128 KiB, total B
*** Warning - bad CRC, using default environment                                
                                                                                
In:    serial@e0001000                                                          
Out:   serial@e0001000                                                          
Err:   serial@e0001000                                                          
Model: Zynq ZC706 Development Board                                             
Board: Xilinx Zynq                                                              
Silicon: v3.1                                                                   
Net:   ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id                        
eth0: ethernet@e000b000                                                         
U-BOOT for xilinx-zc706-2018_3                                                  
                                                                                
ethernet@e000b000 Waiting for PHY auto negotiation to complete....... done      
BOOTP broadcast 1                                                               
BOOTP broadcast 2                                                               
BOOTP broadcast 3                                                               
BOOTP broadcast 4                                                               
BOOTP broadcast 5                                                               
BOOTP broadcast 6                                                               
BOOTP broadcast 7                                                               
BOOTP broadcast 8                                                               
BOOTP broadcast 9                                                               
BOOTP broadcast 10                                                              
BOOTP broadcast 11                                                              
BOOTP broadcast 12                                                              
BOOTP broadcast 13                                                              
BOOTP broadcast 14                                                              
BOOTP broadcast 15                                                              
BOOTP broadcast 16                                                              
BOOTP broadcast 17                                                              
                                                                                
Retry time exceeded                                                             
Hit any key to stop autoboot:  0                                                
Device: mmc@e0100000                                                            
Manufacturer ID: 3                                                              
OEM: 5344                                                                       
Name: SS08G                                                                     
Tran Speed: 50000000                                                            
Rd Block Len: 512                                                               
SD version 3.0                                                                  
High Capacity: Yes                                                              
Capacity: 7.4 GiB                                                               
Bus Width: 4-bit                                                                
Erase Group Size: 512 Bytes                                                     
reading image.ub                                                                
3785300 bytes read in 225 ms (16 MiB/s)                                         
Device: mmc@e0100000                                                            
Manufacturer ID: 3                                                              
OEM: 5344                                                                       
Name: SS08G                                                                     
Tran Speed: 50000000                                                            
Rd Block Len: 512                                                               
SD version 3.0                                                                  
High Capacity: Yes                                                              
Capacity: 7.4 GiB                                                               
Bus Width: 4-bit                                                                
Erase Group Size: 512 Bytes                                                     
reading system.dtb                                                              
15631 bytes read in 16 ms (953.1 KiB/s)                                         
## Loading kernel from FIT Image at 10000000 ...                                
   Using 'conf@system-top.dtb' configuration                                    
   Verifying Hash Integrity ... OK                                              
   Trying 'kernel@1' kernel subimage                                            
     Description:  Linux kernel                                                 
     Type:         Kernel Image                                                 
     Compression:  gzip compressed                                              
     Data Start:   0x10000104                                                   
     Data Size:    3763634 Bytes = 3.6 MiB                                      
     Architecture: ARM                                                          
     OS:           Linux                                                        
     Load Address: 0x00008000                                                   
     Entry Point:  0x00008000                                                   
     Hash algo:    sha1                                                         
     Hash value:   d5d8af69765a88f853ecc91baba385151b747bd2                     
   Verifying Hash Integrity ... sha1+ OK                                        
## Flattened Device Tree blob at 23fff000                                       
   Booting using the fdt blob at 0x23fff000                                     
   Uncompressing Kernel Image ... OK                                            
   Loading Device Tree to 07ff9000, end 07fffd0e ... OK                         
                                                                                
Starting kernel ...                                                             
                                                                                
Booting Linux on physical CPU 0x0                                               
Linux version 4.14.0-xilinx-v2018.3 (oe-user@oe-host) (gcc version 7.3.0 (GCC))1
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d                 
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache        
OF: fdt: Machine model: Zynq ZC706 Development Board                            
bootconsole [earlycon0] enabled                                                 
Memory policy: Data cache writealloc                                            
cma: Reserved 16 MiB at 0x3f000000                                              
random: fast init done                                                          
percpu: Embedded 16 pages/cpu @ef7c9000 s34764 r8192 d22580 u65536              
Built 1 zonelists, mobility grouping on.  Total pages: 260608                   
Kernel command line: console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootp
PID hash table entries: 4096 (order: 2, 16384 bytes)                            
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)                
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)                  
Memory: 1012872K/1048576K available (6144K kernel code, 233K rwdata, 1480K roda)
Virtual kernel memory layout:                                                   
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)                               
    fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)                               
    vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)                               
    lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)                               
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)                               
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)                               
      .text : 0xc0008000 - 0xc0700000   (7136 kB)                               
      .init : 0xc0900000 - 0xc0a00000   (1024 kB)                               
      .data : 0xc0a00000 - 0xc0a3a640   ( 234 kB)                               
       .bss : 0xc0a3a640 - 0xc0a60444   ( 152 kB)                               
Preemptible hierarchical RCU implementation.                                    
        RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.                    
        Tasks RCU enabled.                                                      
RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2                    
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16                                 
efuse mapped to f0802000                                                        
slcr mapped to f0804000                                                         
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000           
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000        
L2C-310 erratum 769419 enabled                                                  
L2C-310 enabling early BRESP for Cortex-A9                                      
L2C-310 full line of zeros enabled for Cortex-A9                                
L2C-310 ID prefetch enabled, offset 1 lines                                     
L2C-310 dynamic clock gating enabled, standby mode enabled                      
L2C-310 cache controller enabled, 8 ways, 512 kB                                
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001                               
zynq_clock_init: clkc starts at f0804100                                        
Zynq clock init                                                                 
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns     
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af02s
Switching to timer-based delay loop, resolution 3ns                             
clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537s
timer #0 at f080c000, irq=17                                                    
Console: colour dummy device 80x30                                              
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.)
pid_max: default: 32768 minimum: 301                                            
Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)                     
Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)                
CPU: Testing write buffer coherency: ok                                         
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000                                
Setting up static identity map for 0x100000 - 0x100060                          
Hierarchical SRCU implementation.                                               
smp: Bringing up secondary CPUs ...                                             
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001                                
smp: Brought up 1 node, 2 CPUs                                                  
SMP: Total of 2 processors activated (1333.33 BogoMIPS).                        
CPU: All CPU(s) started in SVC mode.                                            
devtmpfs: initialized                                                           
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4         
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 191s
futex hash table entries: 512 (order: 3, 32768 bytes)                           
pinctrl core: initialized pinctrl subsystem                                     
NET: Registered protocol family 16                                              
DMA: preallocated 256 KiB pool for atomic coherent allocations                  
cpuidle: using governor menu                                                    
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.     
hw-breakpoint: maximum watchpoint size is 4 bytes.                              
zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000                     
zynq-pinctrl 700.pinctrl: zynq pinctrl initialized                              
e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 26, base_baud = 3125000) is as
`��k˽���[ttyPS0] enabled                                                        
console [ttyPS0] enabled                                                        
bootconsole [earlycon0] disabled                                                
bootconsole [earlycon0] disabled

Облазил все места где можно переконфигурировать uart для вывода, но ничего не получается. Что-то об этом написано на форуме xilinx:

https://forums.xilinx.com/t5/Embedded-Linux/bootconsole-earlycon0-disabled/m-p/749298#M18595

но у меня это хозяйство не работает. После этой модификации банально не собирается devicetree.dtb (не компилится). Еще пробовал в devicetree вносить изменения:

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Thu Mar 11 12:48:50 2021
 */


/dts-v1/;
#include "zynq-7000.dtsi"
#include "zc706.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"
/ {
    chosen {
        //bootargs = "earlycon";
        //stdout-path = "serial0:115200n8";
            bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 nolock rw rootwait ip=dhcp";
                stdout-path = "serial0:115200ns";
    };
    aliases {
        ethernet0 = &gem0;
        i2c0 = &i2c0;
        serial0 = &uart1;
        spi0 = &qspi;
    };
    memory {
        device_type = "memory";
        reg = <0x0 0x40000000>;
    };
};
//#include "system-user.dtsi"

Обратите внимание: в разделе chosen. Это не помогает. Важный момент: нужна rootfs на разделе sd карточки ( /dev/mmcblk0p2 )

Также вопрос: как убрать загрузку по сети (BOOTP broadcast X)? Мне это совершенно не нужно.

Народ, если сталкивался кто - помогите пожалуйста. Вообще ничего не понимаю. Долблюсь над этим долго. С уважением, Константин.

Edited by Kiryanov

Share this post


Link to post
Share on other sites

Для petalinux 2020.1 применял такой патч ядра
(project-spec/meta-user/recipes-kernel/linux/linux-xlnx/xilinx_uartps_patch.patch):

Spoiler

 

From ade2daa9de1c29892bf46817f0b9231172f07711 Mon Sep 17 00:00:00 2001
From: OpenEmbedded <oe.patch@oe>
Date: Thu, 22 Oct 2020 16:09:17 +0300
Subject: [PATCH] Patch for using serial 1 as console device

Signed-off-by: OpenEmbedded <oe.patch@oe>
---
 drivers/tty/serial/xilinx_uartps.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)
 mode change 100644 => 100755 drivers/tty/serial/xilinx_uartps.c

diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
old mode 100644
new mode 100755
index cacca3d3f9dd..a951ec9ab290
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -1485,7 +1485,6 @@ static int cdns_uart_probe(struct platform_device *pdev)
         cdns_uart_uart_driver.nr = CDNS_UART_NR_PORTS;
 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
         cdns_uart_uart_driver.cons = &cdns_uart_console;
-        cdns_uart_console.index = id;
 #endif
 
         rc = uart_register_driver(&cdns_uart_uart_driver);
@@ -1602,8 +1601,10 @@ static int cdns_uart_probe(struct platform_device *pdev)
      * If register_console() don't assign value, then console_port pointer
      * is cleanup.
      */
-    if (!console_port)
+    if (!console_port) {
+        cdns_uart_console.index = id;
         console_port = port;
+    }
 #endif
 
     rc = uart_add_one_port(&cdns_uart_uart_driver, port);
@@ -1616,8 +1617,10 @@ static int cdns_uart_probe(struct platform_device *pdev)
 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
     /* This is not port which is used for console that's why clean it up */
     if (console_port == port &&
-        !(cdns_uart_uart_driver.cons->flags & CON_ENABLED))
+        !(cdns_uart_uart_driver.cons->flags & CON_ENABLED)) {
         console_port = NULL;
+        cdns_uart_console.index = -1;
+    }
 #endif
 
     cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
-- 
2.17.1

 

Ну, и надо включить патч в project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend:

SRC_URI_append += " file://xilinx_uartps_patch.patch"
 

Share this post


Link to post
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

Sign in to follow this